VHDL synthesis error (generic parameters)

[er.akhilkumar]

Hello All,

I am observing a synthesis error while compiling VHDL code using Synopsis design compiler. Actually it is fully generic code in which parameters are like this:

ENTITY abc IS
GENERIC (
A : natural := 4;
B : int_vector(0 TO A-1)
);
PORT (
----
---
--
);

int_vector is an unconstrained array of integers

When I sythesize the code, tool reports "[Error] Name A is unknown". Is this type of generic implementation not synthesizable. The above type of code works fine with simulation tool. Please provide a solution.

Thanx

 

[FvM]

"Referencing Generics in Generic Lists" is an official VHDL 2008 feature, although it may have been granted by some tools previously. Referring to a tool with full VHDL 2008 support is the only reliable solution.

 

[er.akhilkumar]

So, you want to say that this problem is not related with tool, it is related to the VHDL version which we are using?

 

[FvM]

I don't know if your DC version can be configured to support VHDL 2008. Otherwise edit the code.

 

[er.akhilkumar]

I cannot edit the code as I want fully generic block, in which I will only change the parameters nothing else will be changes. Is there any other solution?