sarah23
Newbie level 6
vhdl:
Add_next:hybadd port map(PC_out,(2 => '1',others => '0'),add_next_out);
verilog converted:
hybadd Add_next (PC_out, {2 : 1'b1, {a{1'b0}}}, add_next_out);
i don't understand wat does this means
(2 => '1',others => '0') <==> {2 : 1'b1, {a{1'b0}}}
Add_next:hybadd port map(PC_out,(2 => '1',others => '0'),add_next_out);
verilog converted:
hybadd Add_next (PC_out, {2 : 1'b1, {a{1'b0}}}, add_next_out);
i don't understand wat does this means
(2 => '1',others => '0') <==> {2 : 1'b1, {a{1'b0}}}