Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VHDL Syn in Design Compiler

Status
Not open for further replies.

Aimerbhat

Newbie level 5
Joined
May 14, 2010
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Activity points
1,358
I am using dc with standard LL 130nm library to synthesize a vhdl logic .

I removed the
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
and instead of std logic used bit and bit_vector in intialization
while analyzing in DC
analyze -library work -f vhdl {................}
i get an error
[Error] Expression error: no corresponding "+" operator defined for operand types

i am not able to figure out why this happening


thanks in advance
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top