VHDL Subtype declaration

[Mudugamuwa]

subtype declaration vhdl

I declared a array as follows

type matrix is array (0 to 21) of std_logic_vector(31 downto 0);

I want to make a subtype out of this which has indexes from 0 to 12. Could anyone give me the coding.

 

[keano]

type +subtype declaration vhdl

I declared a array as follows

type matrix is array (0 to 21) of std_logic_vector(31 downto 0);

I want to make a subtype out of this which has indexes from 0 to 12. Could anyone give me the coding.

Subtypes are used restrict ONLY the VALUES that a certain type can take.
So you can't restrict the indexes

 

[Mudugamuwa]

vhdl subtype

Hi,

Got the point! Thanks !!!