VHDL: std_logic_arith VS. numeric_std Problem !!!!!

[omara007]

Hi folks

I'm having a strange problem: Simply, I'm designing a system in VHDL and I'm not using the obsolete (std_logic_arith) package in any of my blocks. At the same time, I had to integrate a 3rd party IP that uses this library. When I instantiated the IP inside my top-level, the top-level compiled smoothly with no error. But, when it came to Elaboration step (I'm using Cadence NC-VHDL), it gave me port type mismatch error !!! ..

Unfortunately, I'm using (numeric_std) library that can't be declared at the same time with (std_logic_arith). So, how can I solve this problem ?

 

[FvM]

Which data type causes the problem? If it's signed/unsigned, the ports can be interfaced as std_logic_vector, using a wrapper.

 

[omara007]

Which data type causes the problem? If it's signed/unsigned, the ports can be interfaced as std_logic_vector, using a wrapper.

Thanks FvM .. I've already done that and it seems working properly now ..