VHDL Simulation warning / Error

[manojrote]

Hi
I have written a simple Reg code and a corresponding test bench in VHDL code. While I compiled I got warnings/errors mentioned below,
Error :
irun: 12.10-s004: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
irun: *E,VHDLTP: VHDL files are being compiled. The utility does not automatically calculate top-level VHDL design units.

Then I have added vhdl ieee package and library files the I got following warnings and errors,

irun: *W,LEXTNV: The suffix (.vhd) found in a libext option was mapped to file type (vhdl) which is not a Verilog type. The suffixes will be mapped to Verilog.
irun: *W,FMDEF: The default file type mapping of .vhd is being overwritten.
ncvlog: *E,EXPMPA (register.vhd,1|1): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
library IEEE;




Can anyone tell me how to resolve the problem???

 

[ThisIsNotSam]

you have to say which module is top.

 

[dpaul]

If I still remember, in irun, you explicitly specify the TOP module name using the -top switch.
There are separate switches to specify Verilog and VHDL files, use them.

These are trivial errors and can be easily solved by reading the user guide.