VHDL simulating a phase shifted clock

[shaiko]

Hello,

I'm trying to simulate a clock that's idle for 113 ns and starts to oscillate at 50Mhz afterwards.
I wrote this code:

process
begin
  case state is
	
    when idle =>
			
      wait for 113 ns ;
      state <= run ;
			
    when run =>
			
      clock <= not clock after 10 ns ;
			
  end case ;	
		
end process ;

When I try to simulate it - the software freezes.

1. Please help me understand the reason of the freeze.
2. What should I change in my code to make it run correctly?

 

[TrickyDicky]

because your process is assigning clock and infinite number of times in a single delta. Remember a process is an inifinite loop. You need wait statements to halt a process.

You might be better off with this code:

---

Code VHDL - [expand]
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process
begin
  wait for 113 ns;
 
  while true loop
    if clk /= '1' then
      clk <= '1';
    else
      clk <= '0';
    end if;
 
    wait for 10 ns;
 
  end loop;
end process;

---

 

[shaiko]

because your process is assigning clock an infinite number of times in a single delta

Why ? Doesn't the "after" keyword take care of the delay?

clock <= not clock [COLOR="#FF0000"]after[/COLOR] 10 ns ;

 

[TrickyDicky]

No. It just shedules the clock assignment. It doesnt halt the process. It then loops around and schedules the assignment over and over, ad infinitem.

 

[shaiko]

No. It just shedules the clock assignment. It doesnt halt the process. It then loops around and schedules the assignment over and over, ad infinitem.

Thanks.

Before I use your suggested code - I want to try and make my own example work...
I changed the original code to:

process
begin

  case state is
	
    when idle =>
			
      wait for 113 ns ; 
      state <= run ;
			
    when run =>
			
      clock <= not clock ;
      wait for 10 ns ;
			
  end case ;	
		
end process ;

This time, simulation doesn't freeze - It works almost as intended - however the first simulated clock edge comes at 226 ns not in 113 ns.
The state changes from "idle" to "run" exactly at 113 ns. But the clock starts oscillating only after another 113 ns.
Why the double waiting ?

 

[TrickyDicky]

signals are not updated until a process suspends. So it goes into idle at time 0. State is scheduled to update on the next delta after waiting 113ns. But it doesnt get to that delta until it hits a wait statement. So it goes back into the idle state, waits another 113ns, at which point state is updated to run.

swap around the wait and state assignment, and it will work as you intend:

state<= run;
wait for 113 ns;

- - - Updated - - -

PS. your code assumes you have given clock an initial value of either '1' or '0'. With my code, any initial value can be used.

 

[shaiko]

General question:
How do you write your main test bench flow?
Do you do it in the form of a state machine?

 

[TrickyDicky]

Not usually.

For this and current VHDL testbenches:
Have a signal called "run_sim" or "ENDSIM" or something. Then you can always have a loop like:

while not ENDSIM loop

- 1 Process for each clock (using the loop above)
- A process for the IP BFM and data generation
- some mechanism to pass the input data to the output
- an OP BFM and checker process.

 

[shaiko]

Thanks.

while not ENDSIM loop

- 1 Process for each clock (using the loop above)
- A process for the IP BFM and data generation
- some mechanism to pass the input data to the output
- an OP BFM and checker process.

If you have a coded example it'll help a lot.

 

[TrickyDicky]

Thanks.
If you have a coded example it'll help a lot.

Not that I can post here.

 

[shaiko]

I see.
Thanks for your help anyway.

I'll keep this post alive with issues I encounter while simulating further.