VHDL simple calculator

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Richard Keno Garvey

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hello guys i would like you guys to help me i am have an assignment. i have to design and implement a Simple Calculator (addition and subtraction)... (multiplication and division would be great also) in VHDL and simulate the operations of this system on a board. please guys help me. i have most addition and subtraction of working as long as the numbers are positive, which is the problem i also need negative numbers. i havent done division and multiplication because if time constraints if you could help with that i would be very greatful 

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
ENTITY midterm0 IS
    PORT ( Num1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         Num2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         key: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         result: out std_logic_vector(3 downto 0);
         GPIO_0: OUT STD_LOGIC;
         GPIO_1: OUT STD_LOGIC);
         END midterm0;
         
        ARCHITECTURE behavior OF midterm0 IS
         BEGIN
            process(num1,num2)
begin
            if (key(0) = '0') then
               result <= (Num1)+(Num2);
               elsif  
               key(1) = '0' then 
               result <= (Num2)-(Num1);
                        
               end if;
            GPIO_0 <= key(0);
            GPIO_1 <= key(1);
                            
            END process;
            
            end behavior;


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
ENTITY midterm1 IS
PORT (result :IN std_logic_vector(3 downto 0);
resultout :OUT std_logic_vector (6 downto 0) );
END midterm1;
ARCHITECTURE behavior OF midterm1 IS
Begin
resultout <= "1000000" when result="0000" else
"1111001" when result="0001" else
"0100100" when result="0010" else
"0110000" when result="0011" else
"0011001" when result="0100" else
"0010010" when result="0101" else
"0000010" when result="0110" else
"1111000" when result="0111" else
"0000000" when result="1000" else
"0010000" when result="1001" else
"1000000" when result="1010" else
"1111001" when result="1011" else
"0100100" when result="1100" else
"0110000" when result="1101" else
"0011001" when result="1110" else
"1000000";
 
END behavior;


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
ENTITY midterm2 IS
PORT (result :IN std_logic_vector(3 downto 0);
resultout1 :OUT std_logic_vector (6 downto 0) );
END midterm2;
ARCHITECTURE behavior OF midterm2 IS
Begin
resultout1 <= "1000000" when result="0000" else
"1000000" when result="0001" else
"1000000" when result="0010" else
"1000000" when result="0011" else
"1000000" when result="0100" else
"1000000" when result="0101" else
"1000000" when result="0110" else
"1000000" when result="0111" else
"1000000" when result="1000" else
"1000000" when result="1001" else
"1111001" when result="1010" else
"1111001" when result="1011" else
"1111001" when result="1100" else
"1111001" when result="1101" else
"1111001" when result="1110" else
"1000000";
END behavior;


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
ENTITY midterm3 IS
PORT (num1 :IN std_logic_vector(3 downto 0);
resultnum1 :OUT std_logic_vector (6 downto 0) );
END midterm3;
ARCHITECTURE behavior OF midterm3 IS
Begin
resultnum1 <= "1000000" when num1="0000" else
"1111001" when num1="0001" else
"0100100" when num1="0010" else
"0110000" when num1="0011" else
"0011001" when num1="0100" else
"0010010" when num1="0101" else
"0000010" when num1="0110" else
"1111000" when num1="0111" else
"0000000" when num1="1000" else
"1000000";
END behavior;


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
ENTITY midterm4 IS
PORT (num2 :IN std_logic_vector(3 downto 0);
resultnum2 :OUT std_logic_vector (6 downto 0) );
END midterm4;
ARCHITECTURE behavior OF midterm4 IS
Begin
resultnum2 <= "1000000" when num2="0000" else
"1111001" when num2="0001" else
"0100100" when num2="0010" else
"0110000" when num2="0011" else
"0011001" when num2="0100" else
"0010010" when num2="0101" else
"0000010" when num2="0110" else
"1111000" when num2="0111" else
"0000000" when num2="1000" else
"1000000";
END behavior;
 

OK im a noob so i kind of understand but im not to sure. if i change what you're saying is that all i have to do i was under the impression that i would have to add something to the decoder part of the code
 

You are using unsigned numbers of course you can't have signed numbers in your calculator.

When making a calculator you should probably be using numeric_std (not: std_logic_arith and std_logic_unsigned) and the signed type for your signals (that are supposed to be numbers)

i.e.
Num1: IN SIGNED(3 DOWNTO 0);

then stuff like Num2 - Num1 will be done using signed (2's comp) arithmetic.

- - - Updated - - -

Richard Keno Garvey said:
OK im a noob so i kind of understand but im not to sure. if i change what you're saying is that all i have to do i was under the impression that i would have to add something to the decoder part of the code
Click to expand...

Don't know what you are doing in the decoder is that some sort of 7-seg driver?

Why are there four midterm# components when you only have a result that has a maximum of 5-bits (Num1 & Num2 are 4-bit which means a 5-bit result...you have a 4-bit result so you have a result that can be 10000, -16 as you have it written -8 + -8 will result in 0). That only requires 2 7-seg digits.
 
thats exactly what it is the maximum number is 14, 7+7 we only had one week to do it so we are keeping it simple. so what i was thinking was i have to program another 7 segment to have a constant - when num2 is larger than num1 during subtraction but thats where i get stuck i dont know what i have to do for it to do the subtraction correctly... u get what im saying?
 


wrong it's (-8) +(-8) or (-8) - (8), which are both -16 or do you mean to restrict the 2's comp inputs numbers to 1001 (i.e. -7)?

How are you showing negative results? Assuming you want signed outputs from the 7-seg.

If you use a 7-seg with only the - (middle segment) lit then you'll have to have three 7-segs not four.
i.e. sign, 10's digit, 1's digit.

I figure the decoder should be one decoder for all three 7-segs (or it can still use three different ones, up to you) that use the same case logic to assign the 7-seg encoding for each digit and sign.

e.g.
Code VHDL - [expand]
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case result is
  when "00000" =>  -- +00
    sign <= "1111111";
    tens <= "1000000";
    ones <= "1000000";
-- ...
  when "10000" =>  -- -16
    sign <= "0111111";
    tens <= "1111001";
    ones <= "0000010";
end case;


- - - Updated - - -

I just realized you may have had four 7-segs for performing multiplication... (-16) * (16) will give you -256 (i.e. four 7-segs)

- - - Updated - - -

If you are going to support multiplication you'll want to have case statements for each digit (one case will be too big), so you'll need to do a binary to bcd conversions first...
https://www.eng.utah.edu/~nmcdonal/Tutorials/BCDTutorial/BCDConversion.html

then use that and a single bcd to 7-seg deccoder, which you'll instantiate 3 times.
 

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