May 17, 2005 #1 S shahsali Newbie level 4 Joined Mar 8, 2005 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,330 How to find out whether Signal A is leading over Signal B and if it is leading then how much it is leading using VHDL.
How to find out whether Signal A is leading over Signal B and if it is leading then how much it is leading using VHDL.
May 18, 2005 #2 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 Here is how you can do it! process (A,B) variable start_A : time; variable leading_by : time; begin if (A'event) then start_A := now; end if; if (B'event) then if (start_A < now) then leading_by := now - start_A; end if; end if; end process;
Here is how you can do it! process (A,B) variable start_A : time; variable leading_by : time; begin if (A'event) then start_A := now; end if; if (B'event) then if (start_A < now) then leading_by := now - start_A; end if; end if; end process;