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vhdl signal generator

hugo92

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Hi my dear friends
I'm working on my home work and i can't understand the question.

Untitled.png


the problem is here:
"
a. When GO changes from ‘0’ to ‘1’ two times consequently, the output UP must go to ‘1’, but T = 10 ms later.
b. When GO changes from ‘0’ to ‘1’ two times but not consequently, the output UP goes to ‘1’ after T=5 ms."

how it is possible that go changes from 0 to 1 two times consequently?
 

FvM

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the problem is here:
"
a. When GO changes from ‘0’ to ‘1’ two times consequently, the output UP must go to ‘1’, but T = 10 ms later.
b. When GO changes from ‘0’ to ‘1’ two times but not consequently, the output UP goes to ‘1’ after T=5 ms."
Unclear. You are describing a requirement or erroneous behavior of your design?
 

hugo92

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it's a part of question. i think the requirement that go changes from 0 to 1 two times consequently is impossible.
 

VeeJayy

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'Go' is just an input signal.

The question just describes a signal which goes to 0 and 1 two times is what I am guessing (Go high, go low, again go high and go low) as per the frequency that 'you' give.

The whole 'two times' that you have mentioned seems to cause the confusion. What exactly are you trying to say?
 

ads-ee

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The description just mentions what happens to the output DOWN if the input GO goes high. The description is poorly worded, but clearly defines the behavior.

Here is a summary of the description, that might make more sense.

The outputs UP and DOWN respond to the input GO as follows:
If GO changes from 0 to 1 then UP changes from 0 to 1 after a 10 ms delay and DOWN is immediately set to 0.
If GO changes from 1 to 0 then DOWN changes from 0 to 1 after a 10 ms delay and UP is immediately set to 0.

When STOP is 1 both UP and DOWN are set to 0 unconditionally.
 

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