VHDL signal assignment error

3wais · Oct 15, 2012

Hi,

I am trying to assign part of a signal to a part of another signal !!
I used this :

Code:

ModDivisor(3) <= Divisor when SelDataSize="000" else 
			(Divisor(31 downto 8) & others =>'0') when SelDataSize = "001" else
			(others =>'0' & Divisor(31 downto 16)) when SelDataSize = "01-" else
			(others =>'0' & Divisor(31 downto 24));

the others keyword in 3rd and 4th lines generates error ..
anyway else to write this ??

TrickyDicky · Oct 15, 2012

There are a couple of problems here:
1. others doesnt work like that, and you cannot use others first (otherwise how does it know what others is?)

Code:

(31 downto 8 => Divisor(31 downto 8), others => '0') when SelDataSize = "001" else
(16 downto 0 => Divisor(31 downto 16), others => '0') when --etc

but given that you know the sizes already, what wrong with constants?

Divisor(31 downto 8) & x"00" when --etc

2. Dont care doesnt work like that. You'll find in simulation, that it wont work unless SelDataSize is actually "01-" , so if its "011" it will fail and hit the last case. You need to use the std_match function:

x"0000" & Divisor(31 downto 16) when std_match("01-", SelDataSize) else --etc

FvM · Oct 15, 2012

An array aggregate like "Divisor(31 downto 8) & others =>'0'" isn't accepted by VHDL. What's against concatenating a zero-vector of defined length in this place?

3wais · Oct 15, 2012

TrickyDicky said:
There are a couple of problems here:
1. others doesnt work like that, and you cannot use others first (otherwise how does it know what others is?)

Code:

(31 downto 8 => Divisor(31 downto 8), others => '0') when SelDataSize = "001" else (16 downto 0 => Divisor(31 downto 16), others => '0') when --etc

but given that you know the sizes already, what wrong with constants?

Divisor(31 downto 8) & x"00" when --etc

2. Dont care doesnt work like that. You'll find in simulation, that it wont work unless SelDataSize is actually "01-" , so if its "011" it will fail and hit the last case. You need to use the std_match function:

x"0000" & Divisor(31 downto 16) when std_match("01-", SelDataSize) else --etc

I have tried this now :

Code:

ModDivisor(3) <= Divisor when SelDataSize="000" else 
			(31 downto 8 => Divisor(31 downto 8), others =>'0') when SelDataSize = "001" else
			(15 downto 0 => Divisor(31 downto 16), others => '0') when SelDataSize = "010" or SelDataSize = "011" else
			(7 downto 0 => Divisor(31 downto 24), others => '0');

when synthesizing it generates this error :

Code:

No array or record type can be found that has elements of types matching the aggregate.

for all the lines that contain this statement !!

I thought it might be a problem with the array definition but it seems right
here is the array definition:

Code:

subtype size1 is STD_LOGIC_VECTOR(NumOfBits downto 0);			
type DivisorSel is array (NumOfStages downto 0) of size1;
signal ModDivisor : DivisorSel;

TrickyDicky · Oct 16, 2012

have you tried the constant aggregate we told you?

divisor(31 downto 8) & x"00"

3wais · Oct 16, 2012

TrickyDicky said:
have you tried the constant aggregate we told you?

divisor(31 downto 8) & x"00"

No , I wanted to find the error in the first code first !!
I will use it now since i have no other choice

should i write a number instead of x ??
meaning 4"00" if i want 0000 0000 for example ??

TrickyDicky · Oct 16, 2012

the x just means hexadecimal representation, so x"FF" means 11111111, x"AB" means 10101011 etc.

Looking at the origional declarations, using a constant may not work properly when the number of bits is changed. To avoid this, it might be best just to wrap this in a process sensitive to SelDataSize, so you can assign the specific parts after assigning the whole array to '0'

eg:

Code VHDL - [expand]
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process(SelDataSize )
begin
  ModDivisor(3) <= (others => '0');
 
  case SelDataSize is
    when "001" =>
      ModDivisor(3)(31 downto 8) <= Divisor(31 downto 8);
 
  --etc

Using this method, with VHDL2008, you can use the matching case statement to use those dont cares properly too:

Code VHDL - [expand]
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process(SelDataSize )
begin
  ModDivisor(3) <= (others => '0');
 
  case? SelDataSize is
    when "001" =>
      ModDivisor(3)(31 downto 8) <= Divisor(31 downto 8);
 
    when "01-" =>
      ModDivisor(3)(15 downto 0) <= Divisor(31 downto 16);
 
  --etc

But bare in mind, you will have to put ALL of ModDivisor in this process, or you will get multiple driver errors.

Also, are you sure you dont mean:

subtype size1 is STD_LOGIC_VECTOR(NumOfBits-1 downto 0);

With the origional code, the size1 type is NumOfBits +1 bits in length.

VHDL signal assignment error

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Code VHDL - [expand]
1 2 3 4 5 6 7 8 9	process(SelDataSize ) begin ModDivisor(3) <= (others => '0'); case SelDataSize is when "001" => ModDivisor(3)(31 downto 8) <= Divisor(31 downto 8); --etc

VHDL signal assignment error

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