VHDL Shift Register/running array

[dareon]

I am trying to program a shift register or running array(32 positions) that I can add one integer to (indexing all the rest of the points down and dropping off the last one), do some math, and then add another point.

Here is a simplified version of the code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NANOPOSITIONER is
Port (
DAC out ports and clock in ports and such... all verified working)

end NANOPOSITIONER;

architecture Behavioral of NANOPOSITIONER is

type int_array is array(0 to 31) of integer;

signal RUNNING_ARRAY1 : int_array;

other signals and processes for ADC/DAC control as well as luts tables.


RUNNING_ARRAY: process (SINE_INT )
begin
for i in 0 to 30 loop
RUNNING_ARRAY1(i +1) <= RUNNING_ARRAY1(i);
end loop;
RUNNING_ARRAY1(0) <= (SINE_INT) ;
end process;

--OUT3 is converted to a std_logic_vector and output via a DAC
-- at the same time I am outputting SINE_INT in the same manner

OUT3 <= DFT_ARRAY1(30);

end Behavioral;

SINE_INT comes from a LUT with 32 points .

Basically I have two sine wave outputs from OUT3 and SINE_INT going to seperate DACs. I would expect if I change the index of DFT_ARRAY1(?) being stored to OUT3 to some other value I should see a phase shift between these waves. It however always stays the same as if all the points in my array actually have the same data.

At this point I am not worried about the math I just want to get the array indexing properly.

Any help is appreciated.

Thank You

 

[FvM]

I should see a phase shift between these waves. It however always stays the same as if all the points in my array actually have the same data.

You get what you told the VHDL compiler:

process (SINE_INT )
begin
for i in 0 to 30 loop
RUNNING_ARRAY1(i +1) <= RUNNING_ARRAY1(i);
end loop;
RUNNING_ARRAY1(0) <= (SINE_INT) ;
end process;

The code is immedediately copying sine_int to all array locations, in other words it declares the array as an alias of sine_int without actually generating registers.

More exactly, it does in synthesis, behaving different in simulation. This happens because you apparently misunderstood the nature of the sensitivity list in a combinational process. Unlike a clocked process, it actually waits for nothing. To generate a delay chain, you have to use a clocked process instead.

process (clk)
begin
if rising_edge(clk) then
  for i in 0 to 30 loop
    RUNNING_ARRAY1(i +1) <= RUNNING_ARRAY1(i);
  end loop;
  RUNNING_ARRAY1(0) <= (SINE_INT) ;
end if;
end process;

 

[vipinlal]

Just wondering, wont the following code copy the LSB bit into the MSB 30 bits?

for i in 0 to 30 loop
RUNNING_ARRAY1(i +1) <= RUNNING_ARRAY1(i);
end loop;

bit 0 first copied to bit 1 first.
then bit 1(which is same as bit 0 now) is copied to bit 2 and so on?

Will the following modification help?

for i in 0 to 30 loop
RUNNING_ARRAY1(31 - i) <= RUNNING_ARRAY1(30 - i);
end loop;

 

[FvM]

Will the following modification help?

It doesn't change anything. Please consider the VHDL rules for update of signals. All registers are updated after a delta cycle.

Would be different for a VHDL variable assignment respectively non-blocking assignment in Verilog.

 

[dareon]

FvM

Thanks for the help that got it working. I was under the mistaken impression that the process would only run once 1 thing in its sensitivity list changed.