C , VERILOG, VHDL.

[maurolarrat]

Hi, friends.

I have a question about incrementing the index of a array of std_logic_vector, and then associating it to a register that are related to an output port of the entity.

The array has 16 elements of (7 downto 0) std_logic_vector.

I hope you can help me to understand what I cant see yet, plese. Thanks.

The state is completely independent from the others:


WHEN s4=>
bus_select <= '1'; -- choose the bus.
TX_send_en <= '1'; -- enable TX module to receive a byte.
data_next <= array_reg(counter_reg); -- pass the byte to a data_reg associated to output port;

IF (counter_reg = 15) THEN
state_next <= 's5'; -- next state when finished sending 16 bytes.
TX_send_en <= '0'; --disable TX module.
ELSE
counter_next <= counter_reg + 1; -- increment the index of the array.
state_next <= 's4'; -- mantain the same state.
END IF;

.........
end process;
...
output <= data_reg; -- data_reg are passed to the output port.