VHDL SDRAM controller

[manuel1139]

sdram vhdl

Hi!

I am going to build an SDRAM controller and asking myself how far this can simplified until at least something can be "seen"?

Is it possible to run, say a 66 MHZ SDRAM, with less speed? (to avoid timing issues in the first time) Or is this the speed that the clock must have?

What wold be absolutely neccesssary to write 1 byte and read it back?

I think I have to do some configuration on the RAM first. Is it possible to read that config word back? Can I check somehow if the RAM is configured correctly ?

How would someone start out such an task? Wich tools do you think are neccessary?

Thanks & best regards
Manuel

 

[Iouri]

vhdl sdram

Hi Manuel,

Firstival I would recommended go to faster spped you can, ie organize pipe lines and constrain your design

SDARM gives you advantages speed and size compare to SRAM, but you have burst cycles for SDRAM you can burst entire page. It means you need to have FIFO internally in your FPGA

Then How to work with SDRAM: 1 initialize, after it goes into IDLE and from idle you can write or read. you will need to make state machine to handle that. When you are making state machine try to use smaller number of stages , in order to achive better performance.


If you give more details about what are you trying to do I can give you more hints how to implemented

Good lack

 

[FrankCh]

sdram controller vhdl

In addition to Iouri's reply, do take note you need refresh cycles as well. That's what extra comparing to simple SRAMs.

Yes you can run at a slower speed, but you need to take care of the refreshing when clock is slowed.