VHDL : resolution function problem

[toninlg]

data_in : INOUT STD_LOGIC_VECTOR(7 downto 0)
signal data : STD_LOGIC_VECTOR(7 downto 0);

Is it normal that the following instruction : data<=data_in; results in a forcing unknown state for data if data_in is in Hi-Z state and data all 0?

The following instructions seems to solve the problem in simulation but I don't know if an Hi-Z state can be detected in hardware?

IF (data_in/="ZZZZZZZZ") THEN data<=data_in;
END IF;

If not what could be the solution?

Thanks a lot.

 

[vvvvv]

How do your real FPGA will know that 'data_in' in 'Z' state
because '111111' it's very similar to 'ZZZZZ'?
You can do this only by measurements, but what for FPGA?

I think you must create additional signal , that will
confirm valid data on data_in :

signal valid_data std_logic:'0' ; '0' data invalid , '1' data_valid

if (valid_data = '1') then data<=data_in ; it's correct string, but asyncronous

More reliable and correct (on rising edge of clk) :

if ( clk'event and clk='1' and valid_data = '1') then data<=data_in

 

[toninlg]

I think I don't understand very well the High-Z state, it's the problem.

By adding additional signal did you mean ie a Write imput? In fact I've got a Write input, but in the simulation if I set data to all 'Z', data_in was forced to unknown. I suppose that like for other IC, data must be valid before the Write signal and that there is nothing to do if Write input is activated while data bus is still High-Z?

 

[vvvvv]

Sorry for my fisrt answer it's not quite correct.

Z-state is high impedance state of output driver .
Output in Z-state isolated from input, the same situation
when you place resistor 10Mom in series from output to
input. All value from output do not reach input.
Next : you have data_in INOUT bus from FPGA to external world
and data = internal signal.
data_in is bus working in INOUT mode that means input
and output connected together.

Why do you use INOUT bus if it's destination only for INPUT data
(judging on name data_in).If so, use IN mode (ie data_in : IN std_logic_vector..)

If it's not, and you need inout bidirectional bus, well go further.
As i said, INOUT means input pin and output driver connected together.


If there is any value on output driver, that the same value you will see
on input. Driver stronger input, you see output value backward on input,
because they connected together.
If you want to see value from external driver connected to your IO pin on
IO bus data_in, you MUST place your output bus to Z state.
If you will not place your output to Z state in worst case external driver
will be fight with you internal output driver. Win strongest. And you will
see result of this fighting on your input data_in.
When your output placed in Z state your output is isolated from input,
and you will see signal from external driver connected to that pin.
That why you must to use Z-state.

Now your data_in in Z-state and you are waiting correct data from external
driver.
If you permanently assign data<=data_in, that 'data' set to unknown state.
Well it's not problem. When you place external data to data_in, do you
have any signal in external pins, which accompanies with valid data .
If you have, not problem. Test this signal and only when that signal
valid, assign data<=data_in.
If you have not such signal, how FPGA define correct data on data_in bus ?

 

[toninlg]

I've to use inout, when Write is enable I update the internal signal data and when Read is enable I put the internal signal data on data_in (name isn't very well chosen but it comes from multiple attempt). There is also a chip select.

If you want to see value from external driver connected to your IO pin on
IO bus data_in, you MUST place your output bus to Z state.

If I use an inout pin how can I place the output bus to Z state? I was thinking that setting data_in to Z state, was the solution to see external data on IO pin?

Here is my code for the block :

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--  Entity Declaration

ENTITY comp IS
	PORT
	(
		clock_20MHz : IN STD_LOGIC;
		CS : IN STD_LOGIC;
		WR : IN STD_LOGIC;
		RD : IN STD_LOGIC;
		INT : IN STD_LOGIC;
		scmpr : OUT STD_LOGIC_VECTOR(6 downto 0);
		sens : OUT STD_LOGIC;
		data_in : INOUT STD_LOGIC_VECTOR(7 downto 0)
		--data_out : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
		
END comp;

ARCHITECTURE f OF comp IS

	signal data : STD_LOGIC_VECTOR(7 downto 0);
	
	BEGIN

	PROCESS(clock_20MHz,CS)
	
	BEGIN
	
			IF (CS='1') THEN
			
				data_in<=(OTHERS=>'Z');
				
			ELSIF (clock_20MHz'EVENT AND clock_20MHz='1') THEN
				
				IF (WR='1' AND RD='0') THEN
					
						data_in<=data;
						
				ELSIF (WR='0' AND RD='1') THEN
					
					data<=data_in;
																
				ELSE data_in<=(OTHERS=>'Z');
									
				END IF;
					
			END IF;
	
	END PROCESS;

	PROCESS (INT)
	
		BEGIN
		
			IF (INT'EVENT AND INT='0') THEN

	scmpr <= data (6 downto 0);
	sens <= data(7);
	
	END IF;
	
	END PROCESS;
				
END f;

 

[tkbits]

Re: VHDL : INOUT port, bidirectional bus

If I use an inout pin how can I place the output bus to Z state? I was thinking that setting data_in to Z state, was the solution to see external data on IO pin?

Yes, the Z state is used to see external data.

-- The SYNC (clocked) portion of this process creates a register
-- to capture the data existing on the bidirectional bus
process (rst, clk)
begin
    if rst = '1' then
        -- reset register
        data_reg <= (others => '0');
    else if rising_edge(clk) then
        -- set register (capture data)
        data_reg <= data_bus;
    end if;
end process;

-- This ASYNC (combinatorial) process creates a three-state buffer
-- that either "connects" the register output to the bidirectional bus
-- or "disconnects" the register output from the bidirectional bus
process (output_enable, data_reg)
begin
    if output_enable = '1' then
        -- connect output to bus
        data_bus <= data_reg;
    else
        -- disconnect output from bus
        data_bus <= (others => 'Z');
    end if;
end process;

 

[darylz]

Why not let it be?
I don't think it is needed to convert z to 1 or 0.

 

[toninlg]

I didn't speak about converting Z to 0 or 1 but detecting if the data bus was High-z. Because in simulation if data bus is High-Z the signal data is forced to unknown. But I was mixing up simulation and real hardware. In hardware if the bus is High-Z the input will see 0, 1 or a value oscillating between 0 and 1.
I don't very well understand how making a bidir bus in VHDL; I've seen some posts upon this subject; I'm not the only thinking it's confused.

 

[tkbits]

You cannot detect High Z. High Z is an overridable state. If one process is continuously driving a signal line to "Z state", then another process can override the state by continuously placing a 0 or 1 on the SAME signal line. You cannot capture a Z state. (You cannot clock it to another signal.) It is an unknown state because its Boolean value is unpredictable.