[SOLVED] VHDL - (real Data type : error 10414)

[saeiddieas]

Hi everybody,
I'm trying to compile this VHDL program in Quartus, but there is an error when I compile it :

Error (10414): VHDL Unsupported Feature error at filehandle.vhd(14): cannot synthesize non-constant real objects or values

This error message is on this line :

signal    dataread : real;

These VHLDs codes are written to reading and writing files in VHDL. But I dont know how can we fix this error?

---

Code VHDL - [expand]
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--include this library for file handling in VHDL.
library std;
use std.textio.all;  --include package textio.vhd
 
--entity declaration
entity filehandle is
end filehandle;
 
--architecture definition
architecture Behavioral of filehandle is
--period of clock,bit for indicating end of file.
signal clock,endoffile : bit := '0';
--data read from the file.
signal    dataread : real;
--data to be saved into the output file.
signal    datatosave : real;
--line number of the file read or written.
signal    linenumber : integer:=1; 
 
begin
 
clock <= not (clock) after 1 ns;    --clock with time period 2 ns
 
--read process
reading :
process
    file   infile    : text is in  "1.txt";   --declare input file
    variable  inline    : line; --line number declaration
    variable  dataread1    : real;
begin
wait until clock = '1' and clock'event;
if (not endfile(infile)) then   --checking the "END OF FILE" is not reached.
readline(infile, inline);       --reading a line from the file.
  --reading the data from the line and putting it in a real type variable.
read(inline, dataread1);
dataread <=dataread1;   --put the value available in variable in a signal.
else
endoffile <='1';         --set signal to tell end of file read file is reached.
end if;
 
end process reading;
 
--write process
writing :
process
    file      outfile  : text is out "2.txt";  --declare output file
    variable  outline  : line;   --line number declaration  
begin
wait until clock = '0' and clock'event;
if(endoffile='0') then   --if the file end is not reached.
--write(linenumber,value(real type),justified(side),field(width),digits(natural));
write(outline, dataread, right, 16, 12);
-- write line to external file.
writeline(outfile, outline);
linenumber <= linenumber + 1;
else
null;
end if;
 
end process writing;
 
end Behavioral;

---

 

[ads-ee]

I'm trying to compile this VHDL program in Quartus, but there is an error when I compile it :

VHDL is not a programming language it's a Hardware Description Language, and Quartus is not the same thing as using GCC to compile software programs.

You can't read and write files in synthesizable code. Synthesis is for building a hardware design. Both the real and the reading/writing files (to a file system on a computer) are not synthesizable to hardware. So the fix is to not put them in synthesizable code.

 

[FvM]

This is typical test bench code that would be used to simulate a design in Modelsim. Why are you trying to compile it in Quartus?

 

[saeiddieas]

:shock:
Thank you so much for this comment and for your time, I just started to learn VHDL.
My objective is to built a hardware design, and I need to implement it with synthesizable codes, may I know is it possible to read the matrix of an image (or just, for the first step a simple matrix which is registered in a text file), by VHDL codes in Quartus?

 

[TrickyDicky]

Yes it is possible VHDL, but you cannot compile it for an FPGA. Quartus is a compiler - not a simulator.

The code you have posted is test code for simulation only - quartus is not a simulator - you want to try modelsim.

 

[saeiddieas]

Thanks for comment.
I do not know at all the difference between the codes able to compile and able to simulate.
I think I have to write this code compilable for an FPGA, but how I can to know it's compilable or not? Is there any reference on web?

 

[K-J]

Thanks for comment.
I do not know at all the difference between the codes able to compile and able to simulate.
I think I have to write this code compilable for an FPGA, but how I can to know it's compilable or not? Is there any reference on web?

Everything written in VHDL can be simulated. To do that you would use a VHDL simulator. Modelsim and GHDL are examples of simulators.

Not everything written in VHDL can be synthesized. Synthesis is the process of taking some description (i.e. the VHDL code) and producing whatever is needed (in this case a bitstream that is used to program a physical FPGA). Quartus is a synthesis tool specific to Altera FPGA devices. Hope this helps.

Kevin Jennings

 

[ads-ee]

I do not know at all the difference between the codes able to compile and able to simulate.
I think I have to write this code compilable for an FPGA, but how I can to know it's compilable or not? Is there any reference on web?

That is where knowing the language by reading the LRM and books helps. I haven't actually seen a comprehensive list of all the VHDL statements that show yes/no/maybe/sometimes synthesizable. If a vendor changes their tool they may add something that is currently not synthesizable.

Given that there are some things that will likely never be synthesizable, such as after delays (usually ignored by synthesis), real data types, and file operations. I suppose a synthesis tool vendor can create library components (e.g. like Synopsys designware) that allows the synthesis tool to recognize a real data type and use some default, like IEEE754 or something, which of course is very resource expensive.

 

[saeiddieas]

Thank you for your comments.
I accept. I think I have to read some books on the subject. I'm doing. I'm trying to do know.
I simulated it with ModelSim, it works well. I want to know how we can make this program synthesizable, and compilable in Quartus.
- If I can't read and write files in synthesizable code, then what's the solution?
- Are these (read and write files) the only incompatible elements, (on these VHDL codes example), for the synthesis of an FPGA?

 

[andre_luis]

- If I can't read and write files in synthesizable code, then what's the solution?

In short words, a simulated code runs within your PC, and a synthesizable code runs within your FPGA. If you want to store data at the HDD of your desktop, your have to implement a non trivial protocol at both sides ( FPGA/PC ), assuming that your board have communication interfaces available.

 

[ads-ee]

Thank you for your comments.
I accept. I think I have to read some books on the subject. I'm doing. I'm trying to do know.
I simulated it with ModelSim, it works well. I want to know how we can make this program synthesizable, and compilable in Quartus.
- If I can't read and write files in synthesizable code, then what's the solution?
- Are these (read and write files) the only incompatible elements, (on these VHDL codes example), for the synthesis of an FPGA?

This seems to indicate you might not understand that hardware only has the interfaces to what you build in hardware. So the concept of a file system doesn't exist unless you actually implement a HDD interface in the FPGA to access a HDD file system. FPGA parts have physical pins that must be connected to something to get data into out of the device. It's not like software programming where you can just use a library like stdio to read/write to the HDD.

I figure you probably don't know how to separate the TEST from the hardware design. Maybe you should give us an overview of what you are trying to accomplish instead of just presenting what you are trying to implement/test with your incomplete understanding of how to test a VHDL hardware design.

 

[TrickyDicky]

That is where knowing the language by reading the LRM and books helps. I haven't actually seen a comprehensive list of all the VHDL statements that show yes/no/maybe/sometimes synthesizable. If a vendor changes their tool they may add something that is currently not synthesizable.

Given that there are some things that will likely never be synthesizable, such as after delays (usually ignored by synthesis), real data types, and file operations. I suppose a synthesis tool vendor can create library components (e.g. like Synopsys designware) that allows the synthesis tool to recognize a real data type and use some default, like IEEE754 or something, which of course is very resource expensive.

I think Kodak wrote it - and it's now part of the VHDL 2008 Standard in the form of the ieee.float_pkg. But it's not supported by the vendors yet (an likely never will be, as they use their IP core libraries). But you can just type convert between SLV and float types easily.

 

[vGoodtimes]

- If I can't read and write files in synthesizable code, then what's the solution?

You would need to treat this like a piece of hardware and find an input. Basically, you need some way to transfer data from your PC to the FPGA. This could be rs232, usb, ethernet, PCIe, etc... If the image is small, you can pre-load the image into block ram during bitstream generation.

- Are these (read and write files) the only incompatible elements, (on these VHDL codes example), for the synthesis of an FPGA?

I don't see your design posted other than the file IO parts. There is little that will synthesize there. For example, "real" typically can only be used for generating constants. all procedures on file/text are out as well. the clock generation is also not possible. (your FPGA dev kit should have an input clock from a pin on the device.) The entity has no outputs, which typically will result in it being synthesized out. It has no inputs either. (While these cases can occur, they are rare in user described logic). The wait statements for clocks are not the preferred style, but I think they do work. You clock the processes on alternating edges of a 500MHz clock, making it unlikely to meet timing in current devices.

 

[saeiddieas]

Thank you everyone :thumbsup: for all comments, I've used your feedbacks.

I'm trying to realize another VHDL code, considering your ideas, in order to read matrix of an image from the memory card.
when I need your help, I will ask you, in a new post.

Friendly