This error message is on this line :Error (10414): VHDL Unsupported Feature error at filehandle.vhd(14): cannot synthesize non-constant real objects or values
signal dataread : real;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 --include this library for file handling in VHDL. library std; use std.textio.all; --include package textio.vhd --entity declaration entity filehandle is end filehandle; --architecture definition architecture Behavioral of filehandle is --period of clock,bit for indicating end of file. signal clock,endoffile : bit := '0'; --data read from the file. signal dataread : real; --data to be saved into the output file. signal datatosave : real; --line number of the file read or written. signal linenumber : integer:=1; begin clock <= not (clock) after 1 ns; --clock with time period 2 ns --read process reading : process file infile : text is in "1.txt"; --declare input file variable inline : line; --line number declaration variable dataread1 : real; begin wait until clock = '1' and clock'event; if (not endfile(infile)) then --checking the "END OF FILE" is not reached. readline(infile, inline); --reading a line from the file. --reading the data from the line and putting it in a real type variable. read(inline, dataread1); dataread <=dataread1; --put the value available in variable in a signal. else endoffile <='1'; --set signal to tell end of file read file is reached. end if; end process reading; --write process writing : process file outfile : text is out "2.txt"; --declare output file variable outline : line; --line number declaration begin wait until clock = '0' and clock'event; if(endoffile='0') then --if the file end is not reached. --write(linenumber,value(real type),justified(side),field(width),digits(natural)); write(outline, dataread, right, 16, 12); -- write line to external file. writeline(outfile, outline); linenumber <= linenumber + 1; else null; end if; end process writing; end Behavioral;
VHDL is not a programming language it's a Hardware Description Language, and Quartus is not the same thing as using GCC to compile software programs.I'm trying to compile this VHDL program in Quartus, but there is an error when I compile it :
Everything written in VHDL can be simulated. To do that you would use a VHDL simulator. Modelsim and GHDL are examples of simulators.Thanks for comment.
I do not know at all the difference between the codes able to compile and able to simulate.
I think I have to write this code compilable for an FPGA, but how I can to know it's compilable or not? Is there any reference on web?
That is where knowing the language by reading the LRM and books helps. I haven't actually seen a comprehensive list of all the VHDL statements that show yes/no/maybe/sometimes synthesizable. If a vendor changes their tool they may add something that is currently not synthesizable.I do not know at all the difference between the codes able to compile and able to simulate.
I think I have to write this code compilable for an FPGA, but how I can to know it's compilable or not? Is there any reference on web?
- If I can't read and write files in synthesizable code, then what's the solution?
Thank you for your comments.
I accept. I think I have to read some books on the subject. I'm doing. I'm trying to do know.
I simulated it with ModelSim, it works well. I want to know how we can make this program synthesizable, and compilable in Quartus.
- If I can't read and write files in synthesizable code, then what's the solution?
- Are these (read and write files) the only incompatible elements, (on these VHDL codes example), for the synthesis of an FPGA?
That is where knowing the language by reading the LRM and books helps. I haven't actually seen a comprehensive list of all the VHDL statements that show yes/no/maybe/sometimes synthesizable. If a vendor changes their tool they may add something that is currently not synthesizable.
Given that there are some things that will likely never be synthesizable, such as after delays (usually ignored by synthesis), real data types, and file operations. I suppose a synthesis tool vendor can create library components (e.g. like Synopsys designware) that allows the synthesis tool to recognize a real data type and use some default, like IEEE754 or something, which of course is very resource expensive.
You would need to treat this like a piece of hardware and find an input. Basically, you need some way to transfer data from your PC to the FPGA. This could be rs232, usb, ethernet, PCIe, etc... If the image is small, you can pre-load the image into block ram during bitstream generation.- If I can't read and write files in synthesizable code, then what's the solution?
I don't see your design posted other than the file IO parts. There is little that will synthesize there. For example, "real" typically can only be used for generating constants. all procedures on file/text are out as well. the clock generation is also not possible. (your FPGA dev kit should have an input clock from a pin on the device.) The entity has no outputs, which typically will result in it being synthesized out. It has no inputs either. (While these cases can occur, they are rare in user described logic). The wait statements for clocks are not the preferred style, but I think they do work. You clock the processes on alternating edges of a 500MHz clock, making it unlikely to meet timing in current devices.- Are these (read and write files) the only incompatible elements, (on these VHDL codes example), for the synthesis of an FPGA?
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