[VHDL] Read Stimuli file in VHDL

[tzushky]

vhdl read

Hello again,

I have been looking throuhg Ashenden's Deisgner Guide to VHDL for file reading in VHDL. I thought it is the best way to drive test becnh signals: have a stimuli file read in the test bench entity and give values to the different needed signals at every clock event.

My problem => my file would contain values for 5 (or more ) signals and they are also of different kinds (enables : std_logic, 8b adresses or data ...)

I arranged them in this waysay for a ram test)

en we addr data q
0 0 00000001 10000001 00000000
1 1 00000010 10000010 00000000

etc... (data is like adress but with MSB=1)

I tried making a file type of a max 8 length vector (the book I mentioned advises that in case different length signal values are found in te file, the read function will have a 3 parameter prototype, read(file, target_vector, length_found). The target_vector is declared as a veriable of max size and normally if a found value is smaller than that length, the vector is filled form left to right. But I tried this on my file and it doesn't work, gives me range error...

I'll show you the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 

entity tb_ram is
end entity tb_ram;

architecture tb_arch of tb_ram is

  constant addr_len : integer := 8;
  constant data_len : integer := 8;

  component sram is
     generic(
        g_addr_length : integer ;
        g_data_length : integer 
     );
    port 
    (
      clk     : in  std_logic;
      en      : in  std_logic;
      we      : in  std_logic;
      a       : in  std_logic_vector(g_addr_length-1 downto 0);
      d       : in  std_logic_vector(g_data_length-1 downto 0);
      q       : out std_logic_vector(g_data_length-1 downto 0)
    );
  end component;
  type  text is file of std_logic_vector;
  file stimulus: text open read_mode is "stimuli.txt";

  signal int_clk: std_logic;
  signal int_we : std_logic;
  signal int_en : std_logic;
  signal int_a:std_logic_vector(addr_len-1 downto 0);
  signal int_d:std_logic_vector(data_len-1 downto 0);
  signal int_q:std_logic_vector(data_len-1 downto 0);
  signal int_verif: std_logic;


  begin


    --instance sram
    tb_i_sram: sram
      generic map(
        g_addr_length =>addr_len,
        g_data_length =>data_len		
        )
		
		
     port map(
        clk     => int_clk,
        en      => int_en,
        we      => int_we,
        a       => int_a,
        d       => int_d,
        q       => int_q
        );

     p_clk: process
     begin
        int_clk<='0';
        wait for 8333 ps;
        int_clk<='1';
        wait for 8333 ps;
     end process;


     recv_data_process:process 

        variable read_len:natural;
        variable str_en	: std_logic_vector(addr_len downto 0);
        variable str_we	: std_logic_vector(addr_len-1 downto 0);
        variable str_a 	: std_logic_vector(addr_len-1 downto 0);--string(g_addr_length);
        variable str_d 	: std_logic_vector(data_len-1 downto 0);--string(g_data_length);
        variable str_q 	: std_logic_vector(data_len-1 downto 0);--string(g_data_length);
        begin
          while not endfile(stimulus) loop
            int_verif<='0';
              
               --first on line: en signal
               read(stimulus, str_en,read_len);
               int_en <= str_en(1);	      
	       
               --we signal
               read(stimulus, str_we,read_len);
               int_we <= str_we(0);	   	       
	       
               --a address  signal
               read(stimulus,str_a ,read_len);	      
               int_a   <= str_a;	     
	       
               --d address  signal
               read(stimulus,str_d ,read_len);	      
               int_d   <= str_d;	      
	       
               --q address  signal check
               read(stimulus, str_q,read_len);	       
               if (int_q   =  str_q) then
                     int_verif <='1';
               end if;      
	       
	       
               wait until int_clk = '1';
             end loop;

             wait;
      end process;
	
end tb_arch;

NCSim error:

ncvhdl: 08.10-p002: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
read(stimulus, str_en,read_len);
|
ncvhdl_p: *E,ALTYMM (../hdl/tb_ram.vhd,85|35): subprogram call or operator argument type mismatch 87[4.3.3.2] 93[4.3.2.2].


Where am I going wrong? I have searched for code examples on the web... I suspect it's the separator of my value sin the text file or... I don't know...

Any ideas?

Thanks in advance,

T

 

[FvM]

vhdl read file

I think, the processing of stimulus file is mainly a matter of text_io package. There are effectively no limitations to convert a present format to make it understandable to your testbench. This package can be used across all simulator platforms.

 

[tzushky]

read vhdl

Could you elaborate a little more?

Doesn't using this package give me a string interpretation of the value sin the file instead of a direct std_logic(_vector) that I need?

Added after 32 minutes:

Plus, I need to use thte Synopsys library obviously, and the std.textio seems to only cover cadence bit-vector like types...

Added after 11 minutes:

Ok, I found the synopsys std_logic_textio library, but I don't seem to find any examples for it....

 

[salma ali bakr]

vhdl read function

You must add the following lines:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;

library STD;
use STD.textio.all;

 

[tzushky]

vhdl stimulus

OK, I finally got it, I was saying silly stuff before, because I thought the textio package in the std library would be replaced by the ieee. std_logic_textio...

Thanks for clearing that up, I also added a line variable in my read process and extract the std_logic vectors I need using the std_logic_textio read function .

Also I needed to delay my verif signal one clock cycle so I added a small process and some intermediary signals to check for my output memory value compared to the one in the file.

Thanks again guys ,

Bye

 

[chetanm]

stimulus vhdl

Hi,

I have used the same code as above and the compilation is successful in ModelSim 6.3c version,
but when i simulate the code im getting an error msg as follows
vsim work.tb_file_read
# vsim work.tb_file_read
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading work.tb_file_read(test)
# Loading std.textio(body)
# Loading ieee.std_logic_textio(body)
# Loading work.txt_util(body)
# Loading work.file_read(read_from_file)
# ** Fatal: (vsim-3633) Index range 4 downto 0 is not compatible with index subtype (1 to 2147483647) of std.standard.string.
# Time: 0 ns Iteration: 0 Instance: /tb_file_read/input_stim File: F:/Xilinx/Xilinx10.1/Projects/ModelSim_Test/File_Handling/VHDL/File_Rd_Wr/RTL/file_read.vhd Line: 11
# FATAL ERROR while loading design
# Error loading design.

has any one have faced similar problem like this.
I would appreciate any comment on this.
Thanks.