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VHDL, questions about register code

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imconfused

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I'm trying to make a 4x8 register bank but I keep getting this error. Did I make this register wrong?

"Index constraint cannot be applied to already-constrained type reg_array" on line 17


Code VHDL - [expand]
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ENTITY Reg4x8 IS PORT(clk,we:    IN std_logic;
     Wr:        IN std_logic_vector (7 downto 0);
     Rdx, Rdy:  IN std_logic_vector (1 downto 0);
     Rx,Ry:     OUT std_logic_vector (7 downto 0));
END Reg4x8;
 
ARCHITECTURE registerBank OF reg4x8 is 
BEGIN
  
first:  PROCESS (clk, we, Wr, Rdx, Rdy)
        TYPE reg_array IS ARRAY(0 to 3) OF std_logic_vector(7 downto 0);
        VARIABLE reg:reg_array(7 downto 0); --------------------------------------LINE 17.
        BEGIN
          
          IF clk'EVENT AND clk='0' THEN
               IF (we='1') THEN 
                    CASE Rdx IS
                         when "00" => reg(0):=Wr;
                         when "01" => reg(1):=Wr;
                         when "10" => reg(2):=Wr;
                         when others => reg(3):=Wr; 
                     END CASE;
               ELSE
                     CASE Rdx IS
                         when "00" => Rx<=reg(0);
                         when "01" => Rx<=reg(1);
                         when "10" => Rx<=reg(2);
                         when others => Rx<=reg(3);
                      END CASE;
                      
                      CASE Rdy IS
                         WHEN "00" => Ry<=reg(0);
                         WHEN "01" => Ry<=reg(1);
                         WHEN "10" => Ry<=reg(2);
                         WHEN OTHERS => Ry<=reg(3);
                      END CASE;
               END IF;
           END IF;
     END PROCESS first;
END registerbank;

 
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barry

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line 17 should be:
variable reg:reg_array;

You don't want the (7 downto 0);
 

TrickyDicky

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To expand on the reason, its because the reg_array type already has declared a fixed size of 4 arrays of 8 bits, so you cannot set a size.
 

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