# [SOLVED]VHDL Programming Help

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#### arve9066

##### Member level 2
Code:
process(rst, adcclock_80Mhz)
begin
if rst = '1' then

time_ack <= '0';
Timestamp <= "11" & "000" & calibration & ADC_Timelog;
time_ack <= '1';
end if;

end if;
end process;

begin

if time_ack = '1' then
timelog <= timelog+1;

if timelog < 64 then
calibration <='1';
elsif timelog > 64 then
calibration <='0';
elsif timelog > 128 then
calibration <='1';
timelog <=0;
end if;
end if;
end if;
end process;

I need to create a signal called calibration that is ON for 64 cycles and OFF for 64 cycles and repeat based on the signal time_ack which is again driven high or low depending on the count of masterclock adcclock_80MHz. The code does not seem to work and the signal calibration always seem to be stuck at 0. I initialize it as 1, so it does the transition to 0 once and then stuck at 0. any idea why?

- - - Updated - - -

Never mind. Stupid question. Fixed it myself. :-|

#### shaiko

Did you try to simulate the above ?
If you didn't - start now.

#### vGoodtimes

The second process has all of the code in the time_ack = '1' branch. this occurs every 8192 cycles.

You want timelog to increment in the else branch, under certain conditions.

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