VHDL Programming Help - MOD_540 Counter

[Gerry_robotics]

Hey Folks,

Need a little help here with my VHDL code.

I'm new to VHDL so please bear with me.

I'm getting the following Error messages for my code posted below. (I'm using the Mentor Graphics "HDL DESIGNER" software package.)
When I run the Design Checker within HDL Designer, the following is displayed:

Line 41: WARNING, Internally generated reset in top design unit 'MOD_540_nty' is not isolated at the top level.

Line 41: WARNING, Synchronous reset of counter 'counter' in top design unit 'MOD_540_nty' is internally generated.

I'm not sure what I'm doing wrong?

Can any of you help me?
See my VHDL code attached.

--
-- VHDL Architecture Lab_01_lib.MOD_540_nty.MOD_540_arch
--
-- Created:
--          by - Gerry - (Video)
--          at - 14:14:52 02/14/2012
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY MOD_540_nty IS
 
PORT( 
sig4 : OUT std_logic;
sig5 : OUT std_logic;
sig6 : OUT std_logic;
sig7 : OUT std_logic;
clk : IN std_logic;
enable : IN std_logic; 
nPor : IN std_logic
    );

    
--set : IN std_logic);   -- Disabled


END MOD_540_nty;

ARCHITECTURE MOD_540_arch OF MOD_540_nty IS
signal counter : std_logic_vector(9 downto 0);    -- 10 BIT Binary counter (1024 states) is needed to count to 539 
BEGIN
    
  
----------------------------------------- COUNTER PROCESS ---------------------------------------------------
-------------------------------------------------------------------------------------------------------------  
  --This is the LINE 41 below in red:  [COLOR=red] 
 process (clk, nPor)[/COLOR]            
 Begin

 if (nPor = '0') then                         -- reset button
    counter <= "0000000000";                   -- set to 0
 elsif (clk'event and clk = '1') then          -- on the rising edge
     if (enable = '1') then                    -- enable signal is "active"
        counter <= counter + 1;                -- count up 1
            if (counter = "1000011011") then   -- when you get to 539 go back to 0
                  counter <= "0000000000";
            end if;
      end if;
 end if;
end process;





--------------------------------------- SignaL Control process -----------------------------------------------
--------------------------------------------------------------------------------------------------------------
process (counter)                                                
begin 
 if (counter >= "0100101100" and counter <= "0101000000") then   -- sig4 goes to Logic LOW between 300 and 320
     sig4 <= '0';
 else
     sig4 <= '1';
 end if;




 if (counter >= "0010111101" and counter <= "0010110100") then -- sig5 goes to Logic LOW between 180 and 190 
    sig5 <= '0';
 else
    sig5 <= '1';
 end if;



 if (counter >= "0010110100" and counter <= "0010111101") then -- sig6 goes to Logic LOW between 180 and 190
    sig6 <= '0';
 else
    sig6 <= '1';
 end if;



 if (counter >= "0010110100" and counter <= "0010111101") then -- sig7 goes to Logic LOW between 180 and 190
    sig7 <= '0';
 else
    sig7 <= '1';
 end if;


end process;
END ARCHITECTURE MOD_540_arch;

Any help would be greatly appreciated.

Thanks
-Gerry

 

[FvM]

Warnings are no error messages. I don't see a particularly problem in the posted design part.

 

[Gerry_robotics]

Warnings are no error messages. I don't see a particularly problem in the posted design part.

Right..... I guess I just worded that incorrectly. Sorry.

Nothing wrong with the code?....... Because when I ran this through a Modelsim simulation, all my outputs remain unchanged.

I set up my input pins accordingly before running the simulation.

clk = Default clock (visible on the waveform)
enable = 1
nPor = 1
counter = HEX output

This was why I assumed something was wrong. It looks like the counter isn't incrementing at all.
See my attached waveform screen capture.

-Gerry

 

[FvM]

The outputs are actually "unchanged", because they stay in 'X' state, the result of missing counter initialization. You need to activate nPOR initially, or use a signal definition with initializer.

signal counter : std_logic_vector(9 downto 0) := (others => '0');

 

[Gerry_robotics]

Fantastic!! I made that change and it worked Flawlessly.

Thanks so much for your help. Chances are I'll have more questions as I go through my
various labs.

Again thanks for your time.

Regards,
-Gerry