vhdl programming doubt

[surerdra]

how to generate 400 hz square signal using 20Mhz fixed clock signal, using simple logic vhdl programming

 

[mrflibble]

Use the PLL / DCM in your fpga. How? Please read the documentation for your fpga, it will tell you all about the PLL / DCM capabilities for your specific fpga.

 

[permute]

Use the PLL / DCM in your fpga. How? Please read the documentation for your fpga, it will tell you all about the PLL / DCM capabilities for your specific fpga.

The minimum PLL internal frequency is too high. maximum division is 128. 400*128 < 80000. 80000 < 400000000. (I don't remember the exact min PLL freq, but I don't think any DCM/MMCM/PLL ever had a min frequency under 100khz)

There are two real solutions. The first is to run the logic at a higher rate, eg 20MHz and use a counter to determine when to toggle signals. This is the clock-enable method The second is to divide the clock using a counter and to feed this to a BUFG. This is discouraged, but the tools will be able to meet hold times and setup times become a non issue. However, there is no longer a good relationship between the fast input clock and the output clock. This is the combinatorial method.

The clock enable method should be preferred, as you can create several divided clocks without using too many BUFG's. The clocks will be related, and timing can be analyzed between them and the fast clock. It can be important if the clocks are used for mid-speed IO. The combinatorial method is discouraged, especially for higher frequencies. It does work at lower frequencies.

 

[mrflibble]

Doh! I am so blind. I read the OP as asking 20 MHz source clock and 400 MHz generated clock.

For 400 Hz I'd probably use DCM to divide it down and then use clock enables. Or maybe just clock enable directly. A 25000-count counter for an 800 Hz toggle rate, maybe a couple of flip flops to fan out, and we have 400 Hz clock enable.

 

[std_match]

how to generate 400 hz square signal using 20Mhz fixed clock signal, using simple logic vhdl programming

What is the purpose for this 400 Hz signal?

If you intend to use it as a clock inside the FPGA, you may be in trouble. You can do it as indicated by permute, but it is then likely that your design can be improved so the 400 Hz clock is not needed.

If it should not be used as an internal clock, you can just use a 25000-count counter, as indicated by mrflibble.

 

[tollinjose]

Why 25000-mod counter ? to get 400 Hz we need 50000-mod counter right ..?

 

[alexan_e]

You have a 20MHz clock , the period is 1/20000000= 50ns , you get one clock edge per period

For 400Hz the period is 1/400 = 2.5ms , you need to change the signal from high to low and low to high every 1.25ms

1.25ms / 50ns = 0.00125/0.00000005 = 25000

 

[mrflibble]

Why 25000-mod counter ? to get 400 Hz we need 50000-mod counter right ..?

A 25000-count counter for an 800 Hz toggle rate, maybe a couple of flip flops to fan out, and we have 400 Hz clock enable.

Toggle the flip-flop at 800 Hz so you get an 400 Hz signal.