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VHDL program NgdBuild:604 error

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ambar686

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hi !! i was designing a full adder using two half adder using the following program, but constantly i got the same error. please help me. any suggestion is acceptable.

the name of vhd file is fulladd.vhd.


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity fulladd is
    Port ( a1 : in  STD_LOGIC;
           b1 : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           car : out  STD_LOGIC);
end fulladd;
 
architecture fullad of fulladd is
component ha
    port(a: in std_logic;
          b: in std_logic;
          sha,cha: out std_logic);
end component;
signal s1,c1,c2:std_logic;
begin
H1: ha port map(a1,b1,s1,c1);
H2: ha port map(s1,cin,sum,c2);
car<=c1 or c2;
 
end fullad;


the ERROR i m getting is:
Code:
[B]ERROR:NgdBuild:604 - logical block 'H1' with type 'ha' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, or the
   misspelling of a type name. Symbol 'ha' is not supported in target
   'xa9500xl'.
ERROR:NgdBuild:604 - logical block 'H2' with type 'ha' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, or the
   misspelling of a type name. Symbol 'ha' is not supported in target
   'xa9500xl'.
[/B]
 

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The reason for this is because you didn't include "ha.vhd" in your project, even if the file exists somewhere in the same directory as "fulladd.vhd".

In some tools, any component that is instantiated that doesn't have vhdl source is assumed to be a blackbox to be resolved later. For example, it may be a built-in primitive, or a synthesized netlist.
 
how to include the ha.vhd in fulladd.vhd? even i have the ha.vhd file in E:\Xilinx\bin\nt\ha this location. and fulladd.vhd in E:\Xilinx\bin\nt\fulladd location.. please help me how to include ha.vhd in fulladd.vhd.
and what is blackbox?
 

I assume you have a project in ISE. add both files to the project using the GUI. For help on using the GUI, see the documentation at xilinx.com or the youtube tutorials from xilinx.

blackbox, in this context, is a component that can't be analyzed during the RTL elaboration. These are typically netlists that have be synthesized by someone else (IP), or blocks that have been synthesized using a different synthesis tool. ngdbuild takes the netlist from the synthesis run along with any other netlists for IP and produces an output that can be used by the implementation portion of the build.
 

click on Project >Add source
then window will appear asking path for source file direct it to E:\Xilinx\bin\nt\ha
click on Add.
 

there is no Add option, it says that it allows only .vhd, .ngc, .ngo file s are allowed. what will i do now? anyone can please tell me the steps i have to used to successfully simulate this program? i am using xilinx ise 9.2i design suite. the xilinx directory is in E:\ drive
 

At left top their is Sources window
click on plus button against fulladd-fullad(fuladd.vhd)
u will find H1 & H2 files missing their by right click on them u can add them.
 

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