ambar686
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hi !! i was designing a full adder using two half adder using the following program, but constantly i got the same error. please help me. any suggestion is acceptable.
the name of vhd file is fulladd.vhd.
the ERROR i m getting is:
the name of vhd file is fulladd.vhd.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladd is Port ( a1 : in STD_LOGIC; b1 : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; car : out STD_LOGIC); end fulladd; architecture fullad of fulladd is component ha port(a: in std_logic; b: in std_logic; sha,cha: out std_logic); end component; signal s1,c1,c2:std_logic; begin H1: ha port map(a1,b1,s1,c1); H2: ha port map(s1,cin,sum,c2); car<=c1 or c2; end fullad;
the ERROR i m getting is:
Code:
[B]ERROR:NgdBuild:604 - logical block 'H1' with type 'ha' could not be resolved. A
pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'ha' is not supported in target
'xa9500xl'.
ERROR:NgdBuild:604 - logical block 'H2' with type 'ha' could not be resolved. A
pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'ha' is not supported in target
'xa9500xl'.
[/B]