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VHDL Program for a 4 bit full-adder

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fm_com_28

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vhdl code for full adder

Dear,
I need a help in writing a VHDL cobe for a 4bit full-adder
regards
 

wvengineer

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vhdl 4 bit adder

I have some VHDL code for a FPGA that incorporated modular design. The first code is a single bit full adder and then the second code is using the previous code to make a four bit four adder. ***Now I did this along time ago and don't remember the quality of it so you're on your own with it ok. You have to have both codes since the second calls the first. Maybe you can use this to get you started. Oh yeah the FPGA was a Xilinx

***Single Bit***

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lab8ex3 is
    Port ( a : in std_logic;
           b : in std_logic;
           cin : in std_logic;
           s : out std_logic;
           cout : out std_logic);
end lab8ex3;
 
architecture Behavioral of lab8ex3 is
 
begin
s<=(a xor (b xor cin)); 
cout<=(b and cin) or (a and cin) or (a and b);
 
end Behavioral;



***Four Bit***

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lab8_final is
    Port ( x : in std_logic_vector(3 downto 0);
           y : in std_logic_vector(3 downto 0);
           s0 : out std_logic_vector(3 downto 0));
end lab8_final;
 
architecture Behavioral of lab8_final is
signal c : std_logic_vector (3 downto 0):="0000";
component lab8ex3 
port(a,b,cin:in std_logic; 
 s,cout:out std_logic);
end component;
 
begin
 
bit1: lab8ex3 port map (a=>x(0), b=>y(0), s=>s0(0), cin=>c(0), cout=>c(1));
bit2: lab8ex3 port map (a=>x(1), b=>y(1), s=>s0(1), cin=>c(1), cout=>c(2));
bit3: lab8ex3 port map (a=>x(2), b=>y(2), s=>s0(2), cin=>c(2), cout=>c(3));
bit4: lab8ex3 port map (a=>x(3), b=>y(3), s=>s0(3), cin=>c(3), cout=>c(0));
end Behavioral;

 
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ss_engg

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may you please mention that how to assign input values of 4 bit adder in vhdl..
is it like that
a<= '0000';

or in another formet.
 

TrickyDicky

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Oh look - another homework assignment.
How about giving it a go yourself.

Btw - the simplest way to do addition in VHDL:

a <= b + c;
 

ss_engg

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when I put the values in test bench then it cause error. then how we put the values in test bench file
 

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