library ieee;
use ieee.std_logic_1164.all;
entity test is
port (
clk : in std_logic;
reset : in std_logic;
);
end test;
architecture behav of test is
signal cntr_done : bit;
signal user_press : bit;
begin
COUNTER_PROC: process(clk, reset)
variable cntr : integer := 0;
begin
if reset = '1' then -- asynchronous reset
cntr := 0;
cntr_done <= '0';
elsif rising_edge(clk) then
-- cntr_done <= '0'; -- 1. the code currently latches the cntr_done = 1, uncomment this if you want cntr_done signal
-- to be a 'tick'
if user_press = '1' then -- 2. count enable
if cntr = 2000 then -- 3. counter will count to 2000
cntr := 0; -- 4. and restart
cntr_done <= '1';
else
cntr := cntr + 1;
end if;
end if;
end if;
end process;