VHDL(procedure)----verilog(task)

[xihushui]

vhdl procedure

this is a procedure in VHDL,but now i want to change it to a task in verilog.how to do it ? stopBitLength is real,is not a in or out(in fact,it is in),how to do in task of verilog?
procedure sout_chk (
numDataBits : integer range 5 to 8;
Txdata : in std_logic_vector(7 downto 0);
ParityBit : in std_logic;
stopBitLength : real;
parityBitExist : boolean;
constant cycleTime : in time;
signal SOUT : in std_logic) is
variable i : integer;
begin
.......
endtask

 

[deva_eda]

task vhdl

Hi,

I guess you are wondering how to pass stopBitLength into verilog tasks? You can do this is two ways

1. If this is the case you can use the "parameter" option in verilog. You can define stopBitLength as parameter and directly use stopBitLength inside the tasks without even declaring them in the task declaration list.

2. You can also use intergers & real data type objects as inputs to the task so in your case you can defineas

task sout_chk;
input integer numDataBits;
input [7:0] Txdata;
input ParityBit;
input real stopBitLength
input boolean parityBitExist;
input SOUT;

begin
...........
end
endtask