Yea I got it.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Gen_Pulse is
Port ( Clock : in STD_LOGIC;
Show_Rand : inout STD_LOGIC :='0';
Write_En : out STD_LOGIC:='0';
Capt_En : out STD_LOGIC:='1');
end Gen_Pulse;
architecture Behavioral of Gen_Pulse is
signal count : integer :=1;
begin
process(Clock)
begin
if(Clock'event and Clock='1') then
count <=count+1;
if(count = 10) then
Show_Rand <= not Show_Rand;
count <=1;
end if;
if(Show_Rand = '0' and count = 10) then
Write_En <= '1';
else
Write_En <= '0';
if(Show_Rand = '1' and count = 10) then
Capt_En <= '1';
else
Capt_En <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
tb
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Gen_Pulse
PORT(
Clock : IN std_logic;
Show_Rand : INOUT std_logic;
Write_En : OUT std_logic;
Capt_En : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
--BiDirs
signal Show_Rand : std_logic;
--Outputs
signal Write_En : std_logic;
signal Capt_En : std_logic;
-- Clock period definitions
-- constant Clock_period : time := 1us;
-- constant Show_Rand_period : time := 1us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Gen_Pulse PORT MAP (
Clock => Clock,
Show_Rand => Show_Rand,
Write_En => Write_En,
Capt_En => Capt_En
);
clock1_process
rocess
begin
Clock <= '0'; --reset<='1';
wait for 10ns;
Clock <= '1'; --reset<='1';
wait for 10ns;
end process;
END;