indoubt
Newbie level 1
Hi everybody. I'm have to implement a testbench for a sign-mag adder in a college project, but im having problems.
I can do the analysis and the elaboration without any problems, however when i try to execute the files i receive the message
I can do the analysis and the elaboration without any problems, however when i try to execute the files i receive the message
Im new to vhdl, so i don't have any idea how to solve it."../../src/ieee/numeric_std-body.v93:1005:70msassertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE"
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