signal count :std_logic_vector(1downto0):="00";-- Enumerated type declaration and state signal declarationtype States is(S0,S0a, S1, S2, S3,S4);signal nState, cState: states;begin
state_reg:process(clk, Reset)beginif(Reset = '1')then
cState <= S0;elsif(clk'eventand clk = '1')then
cState <= nState;endif;endprocess;
comb_logic:process(cState)-- variable count : integer range 0 to 7:= 0; begincase cState iswhen S0 => counter <="00";
Strobe <= '0';if(count <"11")then
count<= count +"01";
nState <= S0;else
nstate <= S1;
count <="00";endif;when S1 => counter <="01";
Strobe <= '0';
nState <= S2;
Hi there
my problem here is I want to introduce a delay of about 3 cycles for state to go from S0 to S1; I have introduced count to do that. But even if I use it as a signal or variable; I am unable to increment count and if statement doesn't become true and I am unable to go to next state.
If you could please help me debug what I am doing wrong; it would be great
Put the counter in a clocked process - you cannot do a counter in a combinatorial process. It is not updating because you forgot to add count to the sensitivity list, but if you do, you'll get an infinite loop because counters cannot be incremeneted combinatorially.
I, for one, never use separate clocked/combinational process for state machines. I know all the literature says this is the way to do it, but I find it's always a problem (just like what you're seeing here).
So, as was previously stated, put the counter in a clocked process, and use ieee.numeric_std
Untested but your code should be something like this for a counter using your 2 process FSM style.
Code VHDL - [expand]
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if(Reset = '1')then
Count <=(others=> '0');elsif rising_edge(clk)then-- this is the recommended way to detect a rising edge it only triggers if transition is 0 => 1.if cState = S0 and Count <"11"then-- it has to be done when your FSM is in the S0 state
Count <= Count +"01";else
Count <=(others=> '0');endif;endif;