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VHDL Problem, Can anyone help me?

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Hyro

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I'm new to VHDL so i'm still trying to get to know the basics. What I'm having problems with is a 8-bit DFF(Flip Flop) what i'm trying to do is recreate this program 6 times so that when the 8-bits go in it hold them till a total of 32-bits are held then release to a single output. I keep getting the same error:

ERROR:HDLParsers:164 - Line 43. parse error, unexpected TICK

Component:(J_DFF)

entity J_DFF is
Port ( D : in STD_LOGIC_VECTOR(7 DOWNTO 0);
Q : out STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK : in STD_LOGIC;
RESET : in STD_LOGIC);
end J_DFF;

architecture Behavioral of J_DFF is

Begin

process (CLK, RESET)
begin
if RESET = '1' then Q <= '00000000' ; -- Error is here !
elsif (CLK'event and CLK='1') then
Q <= D;
end if;
end process;

end Behavioral;

---------------------------------------------------------------

To recreate it 6 times this program was created:

entity 8DFF is
Port ( D : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic);
end 8DFF;

architecture RTL of 8DFF is

component J_DFF is
Port ( D : in std_logic_VECTOR(7 downto 0);
Q : out std_logic_VECTOR(7 downto 0);
CLK : in std_logic;
RESET : in std_logic);
end component;

begin

structure: FOR i IN 0 TO 5 GENERATE
DFFi: J_DFF port map(D => D(i), Q => Q(i), CLK => clk, RESET => reset );
END GENERATE;

end RTL;

--------------------------------------------------------------------

Thanks if anyone can help!
 

Tick ( ' ) is used for single bits. For vector use " :
Q <= "00000000"
 
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    Hyro

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Thanks it works now
 

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