VHDL Port mapping doubt

[hithesh123]

Revising VHDL, but confused about port mapping.

This is from Mark Zwolinski's book -

architecture netlist2 of comb_function is
component And2 is
port (x, y : in BIT; z: out BIT);
end component And2;
component Or2 is
port (x, y : in BIT; z: out BIT);
end component Or2;
component Not1 is
port (x : in BIT; z: out BIT);
end component Not1;
signal p, q, r : BIT;
begin
g1: Not1 port map (a, p);
g2: And2 port map (p, b, q);
g3: And2 port map (a, c, r);
g4: Or2 port map (q, r, z);
end architecture netlist2;

In g1, g2, g3, g4 instances, a, b and c are used but they are no where declared. Is this correct?

 

[FvM]

In g1, g2, g3, g4 instances, a, b and c are used but they are no where declared. Is this correct?

Yes, your code is only the architecture part of a design. a,b,c and z are obviously ports of the design, declared in entity part that is missing.

P.S.: Just turn one page back to entity comb_function.