vhdl package in altera quartus II

[soloktanjung]

code for a mux4 in altera

hi ,

i want to build 16 to 1 mux with 4 to 1 mux. therefore I need to create package for 4 to 1 mux.

the code is as below:

library IEEE;
use IEEE.std_logic_1164.all;

PACKAGE mux4to1_package IS

COMPONENT mux4to1 IS
PORT (x0, x1, x2, x3 : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC);

END COMPONENT;
END mux4to1_package;


when I compile it, I got an error.

anything wrong with the code?

hairo