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VHDL out of range error

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sangitacp93

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Hello all,

While doing behavioral simulation, there is an error which says '
[VRFC 10-1537] value -3 is out of target constraint range 0 to 2147483647 ["C:/Users/S/SineDDS/SineDDS.srcs/sources_1/new/Sine.vhd":57]
and
[XSIM 43-3321] Static elaboration of top level VHDL design unit dds_sine_tb in library work failed.


All the vector length used here is 4(3 downto 0)

Two doubts:
1. The range says 0 to 2147483647 , but I am using only 0 to 15(2**4)
2. The value -3. Sine

Please do suggest if there is any more changes for this. I am generating sine value array.

Thank you.

Code:
architecture rtl of dds_sine is
constant C_LUT_DEPTH    : integer := 2**4;
constant C_LUT_BIT      : integer := 4;    

type t_lut_sin is array(0 to C_LUT_DEPTH-1) of std_logic_vector(C_LUT_BIT-1 downto 0);
-- generate sine value
function init_lut_sin return t_lut_sin is
variable v_sin_table    : t_lut_sin:=(others=>(others=>'0'));
variable v_tstep       : real :=0.0;
variable v_sine_sgn   : std_logic_vector(C_LUT_BIT-1 downto 0):=(others=>'0');
constant c_step          : real := 1.0/real(C_LUT_DEPTH);

begin
  for index in 0 to C_LUT_DEPTH-1 loop
    v_sine_sgn := std_logic_vector(to_unsigned(integer(round(2.0**(C_LUT_BIT-1)*sin(MATH_2_PI*v_tstep))),C_LUT_BIT)); --(sin (2PI/2^n)) --line:57
    v_sin_table(index)  := v_sine_sgn;
    v_tstep := v_tstep + c_step;
     end loop;
     return v_sin_table;
end function init_lut_sin;
 
Last edited by a moderator:

These are two totally separate issues. The out of range error is, as it says, because you're trying to assign a value (-3) which is outside the range of what you're trying to assign it to. (If you showed line numbers that would be a BIG help). My guess is that the problem is where you've got about 200 conversions going on: std_logic_vector/unsigned/integer/sin...

You say "The range says 0 to 2147483647 , but I am using only 0 to 15(2**4) ". Why do you think that? You've got integers, which are -2147483648 to +2147483647 and you've got reals. I'd suggest breaking that equation for v_sine_sgn into separate steps and see where the error occurs.

The second error (elaboration) indicates there's some problem in dds_sine_tb, which we have no clue about. What is it? Is that the module you're showing us, or something else? Maybe it's related to the first problem; fix that one first.
 
Hello Barry,

Thank you. I tried a workaround with your suggestion, but I wasnt quite successful in that.
After I break the conversions, I landed up with other errors.

I am somewhere messing up the the data types and arrays.

Its the same error

Simulation error:
[Synth 8-318] illegal unconstrained array declaration 'v_conv_sin' ["C:/Users/Sangita.POKHREL/SineDDS/SineDDS.srcs/sources_1/new/Sine.vhd":52]

Synthesis error:
[VRFC 10-1537] value -3 is out of target constraint range 0 to 2147483647 ["C:/Users/S/SineDDS/SineDDS.srcs/sources_1/new/Sine.vhd":58]


47 type t_lut_sin is array(0 to C_LUT_DEPTH-1) of std_logic_vector(C_LUT_BIT-1 downto 0); 48 -- generate sine value 49 function init_lut_sin return t_lut_sin is 50 variable v_sin_table : t_lut_sin:=(others=>(others=>'0')); 51 variable v_tstep : real :=0.0; 52 variable v_conv_sin : unsigned; 53 variable v_sine_sgn : std_logic_vector(C_LUT_BIT-1 downto 0):=(others=>'0'); 54 constant c_step : real := 1.0/real(C_LUT_DEPTH); 55 56 begin 57 for index in 0 to C_LUT_DEPTH-1 loop 58 v_conv_sin := to_unsigned(integer(2.0**(C_LUT_BIT-1)*sin(MATH_2_PI*v_tstep)),C_LUT_BIT); 59 v_sine_sgn := std_logic_vector(v_conv_sin);--(sin (2PI/2^n)) 60 v_sin_table(index) := v_sine_sgn; 61 v_tstep := v_tstep + c_step; 62 end loop; 63 return v_sin_table; 64 end function init_lut_sin;
 

I would start with the first problem. You are trying to convert a negative sine value to a unsigned number. Try signed.
 
the first post has an error because the full sine wave is attempted to be put into the LUT, but the code is written for only non-negative values. either change this to use signed values, change this to have an offset, or use a quarter-wave LUT.
 
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