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VHDL or Verilog?Which one is better?

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sinaiee

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Hi.I want to start Verilog or VHDL.Which one is better?Why?
 

wolfheart_2001

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TAKE MY ADVICe and start with VHDL because:

1-easy to learn.
2-more logical to imagine and to understand.
3-simple coding.
4-many books,resources and compilers support VHDL.

This is from my point view.

if you are good in programming with C so you can also go with verilog.

good luck
 

    sinaiee

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jiveshgovil

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    sinaiee

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luck4you

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According me its better to learn Verilog as it is very much adopted in Industry.
 

willyboy19

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My background is mainly analog IC design, but I need to do some RTL digital design/implementation from time to time. Based on my experience, Verilog is definitely the better HDL language to use: 1) Simpler to learn; 2) Less stringent syntax requirement; 3) Much more widely adopted in the industry.

A strong vote for Verilog!
 

    sinaiee

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suvendu

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VHDL is better to start.but verilog is easy to learn if u know c language a bit.
READ the book by J.BHASKAR.the book is also in this forum. it is helpful for u.
 

    sinaiee

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alijan

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thanks, but which one is powerfull?
 

    sinaiee

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wolfheart_2001

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some people are more related to verilog coz they already started with verilog and never tried to learn vhdl seriously...i tried to code with both languages and i still insist that vhdl is much more better coz it was the first hdl language to be used so it has been enhanced to its best...in fact the most important thing in hardware programming language is, does it help you to imagine your design?...VHDL is perfect in that but verilog is like C language and you cant imagine your design very well..VHDL is more restricted in the assignments so errors are much less...you will find 50% of engineers use VHDL and 50% use verilog..and who say that verilog is more adopted in industry than VHDL knows nothing.
 

electron_boy

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people who start with vhdl say vhdl is easy to learn...but the truth is when u know any one HDL it is easy to learn the other...i started with vhdl and i find easy to understand verilog... that happens for verilog people too... i think many will agree with this...

u cant say one is powerful than the other...with verilog u can even model at gate level...but both are well suited for industry...and the industry is using both... so u can start with either...my suggestion would be vhdl bcoz i did that way...if there is a requirement for verilog, it will take not more than a week to learn verilog.... u can trust me...

...electron boy
 

SkyHigh

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Being working with ASIC for over 5 years, maybe I can offer a better advice on VHDL and Verilog.

If you are working at the top abstraction level where you work with functional simulation, modelling and RTL development, either VHDL or Verilog, there is strictly no difference. It depends on your experience in "thinking" and interpreting digital hardware in the logical manner.

If you work with Cadence Silicon Ensemble or NanoEncounter for Floorplan, Place-and-Route, you have to generate your gate-level netlist in Verilog from Synopsys or other logic synthesis tool. This is because Cadence, due to commercial reason as Cadence owns Verilog and supports its own SystemVerilog programme, designers are quite forced to stick with Verilog.

If you use other tools, such as MentorGraphics, TI Pyramid, etc, you can export your gate-level netlist in VHDL.

Personally I think it is easier to write testbenches with Verilog. It has better functions in reading testvectors.
There is problem in Verilog. Because it is frequent in many aspects to use Wire and Reg, if you encounter a hardware design where high-speed bus is required, synthesis tool can specify it as strong logic 1 or logic 0 signal, which is practically and realistically untrue because high-speed bus signals are almost so weak and close to switching threshold that it is quite like a triangle or sawtooth or distorted.
This is not the case with VHDL. With its strict and well-organised standard logic vectors with 9 defined levels, it resolves this issue that Verilog can only pray the hardware will work after tape-out.

Verilog is very much like C lang. Therefore it lacks rules to confine how a good RTL description should be styled. VHDL has strict rules to make sure that ASIC designers using VHDL will learn the right way from the beginning.

I think I have given my fair share on VHDL and Verilog.

Two things to add: US Defence Research DARPA uses only VHDL for defence projects. Perhaps it might be a hint that VHDL is a more robust HDL to use.
ChipIdea, a very strong multimedia ASIC company, selected by Microsoft to design the hardware for XBOX 360, uses VHDL and no Verilog.
Europe uses VHDL partly because the US Defence Research DARPA uses VHDL. Indications like such is quite clear that VHDL has reasons for very important roles above Verilog.
 

Willt

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I've asked such question before. For some reasons, I've learned both VHDL and verilog.

In my opinion, Verilog is easier to learn. You could l pick it up within a few days or a week. VHDL is more difficult with strange syntax and complicated (I think) but more powerful than Verilog. (There is no free lunch in this world!)

Also, learning which HDL depends very much on the country you're living in. If most of the companies in your country use EDA tools related to verilog, you have to learn verilog, and the same for VHDL.

Hope it helps ~

Will
 

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