Hi All;
VHDL or Verilog: What is best for nested generate statement? I need some complex nested generate statement in verilog or VHDL. But Whic is better?
but when i try to synthesize this code i have got some errors:
ERROR:HDLCompilers:187 - "Generator_tree_DP.v" line 241 Index in bit-select of vector wire 'downDOut0' is undefined
ERROR:HDLCompilers:96 - "Generator_tree_DP.v" line 241 Connection to input port 'd0in' is illegal
ERROR:HDLCompilers:187 - "Generator_tree_DP.v" line 242 Index in bit-select of vector wire 'downUIn0' is undefined
ERROR:HDLCompilers:102 - "Generator_tree_DP.v" line 242 Connection to output port 'u0out' must be a net lvalue
Both languages provide generate constructs, no one would choose the HDL due to it's generate features.
As for the syntax error in your code snippet, please provide meaningful code including the referenced variable or parameter definitions, and a complete checkable generate statement.