Hello,
I had a component in my VHDL design. some ports of this component are not needed to be connected. I have used 'open' in port map section. This works ok for ports of mode out. for ports of mode in, I have to set initial value for the port first. As an example
Code:
Component HalfAdder
Port (
Clk : in std_logic;
Rst: in std_logic;
In_1: in std_logic;
In_2: in std_logic := ‘1’ ;
Carry: out std_logic;
Sum : out std_logic
);
End component;
ModifiedAdder: HalfAdder
Port map (
Clk => clk,
Rst => rst,
In_1 => In_1,
In_2 => open,
Carry => open,
Sum => sum
);
My question, Why I have to initialize the input ports. i.e why I can't leave it open without assigning initial value?
Input ports cannot be left unconnected according to the IEEE specification. All inputs must be driven.
If you are not assigning any value to the inputs it will lead to error value propagation in the design.