VHDL of Memory arrays

[kongruxue]

Hi , I have to write VHDL code of a memory.

the function is :
there just 2 states,read and write.
if we=1 , the data is wrote into the memory, otherwise it always shows read state ,that means the data_out shows the data which are stored in the memory.

There 5 input:
clock, enable, write(we), data_in (width of d bit),address (width of c bit)
and one output :
data_out (width of d bit)



I have to use unit of memory cell which can only save 1 bit (I was told to use RS-flip flop which I don’t know how) and unit Demux to build the whole memory. Without use ram block which already in FPGA existed.

Does anyone can help me or give me some ideas?

 

[gongdori]

If you have Xilinx ISE or Altera Quartus II, you can get templates of VHDL, Verilog building blocks from the tool.
Here is an example for flipflop:

process (<clock>)
begin
   if <clock>'event and <clock>='1' then  
      if <reset>='1' then   
         <output> <= '0';
      else
         <output> <= <input>;
      end if;
   end if;
end process;