library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity DFF is
port(D : IN signed (7 downto 0);
Clk : in std_logic;
Q : OUT signed (7 downto 0));
end DFF;
architecture behavior of DFF is
begin
process (Clk) -- Change of Clk .
begin
if (Clk'event and Clk='1') then -- Clk event and positive edge. (Change Clk=?0? for negative edge)
Q <= D;
end if;
end process;
end behavior;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity RaderExample is
Port (x1 : IN signed (7 downto 0);
x2 : IN signed (7 downto 0);
Clk : in std_logic;
C : OUT signed (7 downto 0));
end RaderExample;
architecture Behavioral of RaderExample is
component DFF
port(D : in signed (7 downto 0);
Clk : in std_logic;
Q : out signed (7 downto 0));
end component;
signal sDFF1 : signed (7 downto 0);
begin
DFF1 : DFF port map (sDFF1,Clk,C);
CLK_PROC : process (Clk)
begin
if rising_edge(clk) then
sDFF1 <= (x1 sll 1) + (x2 sll 2);
end if;
end process CLK_PROC;
end Behavioral;