VHDL not showing output of shift register

[ghattasak]

hello there i have written the following in VHDL a code for a rotating registers should start with 1000 then rotate then 1 with each cycle 0100 0010 0001
the problem is i am not getting any output on the output bus
can anyone help?

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Code VHDL - [expand]
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entity writeren is
generic (M: integer:=4);
    port(
        clk, reset: in std_logic;
        wr_en: in std_logic;
        wr_a: inout std_logic_vector(((M/2)+1) downto 0)
        );
end writeren;
 
architecture loadreg of writeren is
 
begin
 
process (clk, reset)
    begin
    
        if (reset = '1') then
            wr_a(0)<='1';           
            wr_a((M/2)+1 downto 1)<=(others=>'0');
 
        elsif (clk'event and clk = '1') then
            if (wr_en = '1') then
                wr_a(((M/2)+1) downto 0) <= wr_a(0) & wr_a((M/2)+1 downto 1);               
            end if;
        end if;
        
    end process;
end loadreg;

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[TrickyDicky]

Its working just fine for me. Show us the waveform you're getting.

One question - why have you declared wr_a as inout? you should not use inout just to read the value back. You need to either:

1. declare wr_a as buffer
2. decalre wr_a as out and use an internal temporary signal.

 

[ghattasak]

https://obrazki.elektroda.pl/7820403300_1373281822.jpg
this is my waveform i have changed the type to buffer and can u show me an example of an internal temp signal plz?

- - - Updated - - -

ok i understood the error was i wasnt hitting reset to initialize i should initialize without the reset in code

- - - Updated - - -

i have added the following statement but it is not intializing
architecture loadreg of writeren is

begin

wr_a(0)<='1';
wr_a((M/2)+1 downto 1)<=(others=>'0');

process (clk, reset)
begin

 

[FvM]

I don't understand the purpose of defining the shift register as inout port. The port is unconditionally driven, so it can never operate as an input.

 

[TrickyDicky]

internal signal:

wr_a : out std_logic_vector

....

architecture rtl of a is
  signal wr_a_i : std_logic_vector(wr_a'range);
begin


  process(clk, reset)
  begin
    --assign wr_a_i instead of wr_a;
  end process;

  wr_a <= wr_a_i;

And you cannot initialise it that way outside of a process, because you then get multiple drivers. The process wants to shift, while the assignment wants to always drive '0' or '1' on the signal. So you get conflicts. Just reset it properly, or give it an initial value at signal assignment:

signal wr_a_i : std_logic_vector(wr_a'range) := (others => '0');

 

[AdvaRes]

Hi,
Try to force reset to 0. It should work.
If the problem persists use the else for the inout output assignement:
wr_a(((M/2)+1) downto 0) <= wr_a(0) & wr_a((M/2)+1 downto 1) else (others => 'Z');

Generally an inout employs a control signal to select the direction of a signals. If data is a inout port and considering the direction signal oe we use it data as below:
titi <= data when oe = '0' else (others => '0');
Else here is not mandatory.
For output:
data <= tata when oe = '1' else (others => 'Z');
Here else is obligatory
@FVM
With inout, the shift register can be used as a parallel to serial converter

 

[FvM]

With inout, the shift register can be used as a parallel to serial converter.

It can't unless you release the shift register feedback conditionally and drive the port to high Z.

The inout code can be understood to model two different kinds of hardware, I think:
- a real bidirectional port of the top entity. Then it won't work without a register besides wr_a that holds the internal state.
- a "virtual" internal bidirectional bus. Then wr_a can be possibly a register with it's input multiplexed between two sources. Can only work if the sources are driven mutually exclusive to the bus, controlled by the same clock and multiplex signal.

 

[ghattasak]

thank you i have switched the type from inout to buffer and added an initial reset to the state machine in order to assign the values