--example:
--a<= x"FE";
--same as
--a<= "11111110";
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ASCII is
PORT (getfromreceiver: in std_logic_vector(7 downto 0); -- receiver sends the 8bits of ascii BINARY
clk : in std_logic;
clr: in std_logic;
sendtotransmitter: out std_logic_vector(7 downto 0); -- translate word by word to the transmitter
dready_receiver: in std_logic;
dready_transmitter: out std_logic
);
END ENTITY ASCII;
architecture design of ASCII is
signal datain: std_logic_vector(7 downto 0);
signal reg: std_logic_vector(7 downto 0);
type possiblestates is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal next_state: possiblestates;
BEGIN
FSM: process(clk,clr,getfromreceiver)
--variable datain: std_logic_vector(7 downto 0):= (others => '0');
BEGIN -- S0 is the default state which will remains in the Non-valid char as long as no match occurs
if (clr = '1') then
datain <= (others =>'0');
elsif(clk'event and clk='1') then
if dready_receiver ='0' then
datain <= getfromreceiver;
if (datain = x"3C") then -- less sign
next_state <= S1;
elsif (datain = x"3D") then -- equal sign
next_state <= S2;
elsif (datain = x"3E") then --greater sign
next_state <= S3;
elsif (datain = x"26") then -- And symbol
next_state <= S4;
elsif (datain = x"7C") then -- OR symbol
next_state <= S5;
elsif (datain = x"2B") then --addition
next_state <= S6;
elsif (datain = x"2D") then --subtraction
next_state <= S7;
elsif (datain = x"2A") then --multiplication
next_state <= S8;
elsif (datain = x"2F") then --division
next_state <= S9;
else
next_state <= S0; --"Non-valid char"
end if;
end if;
end if;
end process;
OUTPUT: process(clr,next_state)
begin
if(clr='1') then
reg <= (others => '0');
elsif (clk'event and clk='1') then
--dready_transmitter <= '0'; -- the transmitter is detecting the falling edge signal
case next_state is
--LESS
when S1 => reg <=x"4C";
reg <=x"65";
reg<=x"73";
reg<=x"73";
reg<=x"0D";
reg<=x"0A";
--EQUAL
when S2 => reg <=x"45";
reg <=x"71";
reg<=x"75";
reg<=x"61";
reg<=x"6C";
reg<=x"0D";
reg<=x"0A";
--GREATER
when S3 => reg <=x"47";
reg <=x"72";
reg<=x"65";
reg<=x"61";
reg<=x"74";
reg<=x"65";
reg<=x"72";
reg<=x"0D";
reg<=x"0A";
--AND
when S4 => reg <=x"41";
reg <=x"6E";
reg<=x"64";
reg<=x"0D";
reg<=x"0A";
--OR
when S5 => reg <=x"4F";
reg <=x"72";
reg<=x"0D";
reg<=x"0A";
--Addition
when S6 => reg <=x"41";
reg <=x"64";
reg<=x"64";
reg<=x"69";
reg<=x"74";
reg<=x"69";
reg<=x"6F";
reg<=x"6E";
reg<=x"0D";
reg<=x"0A";
--Subtraction
when S7 => reg <=x"53";
reg <=x"75";
reg<=x"62";
reg<=x"74";
reg<=x"72";
reg<=x"61";
reg<=x"63";
reg<=x"74";
reg<=x"69";
reg<=x"6F";
reg<=x"6E";
reg<=x"0D";
reg<=x"0A";
--Multiplication
when S8 => reg <=x"4D";
reg <=x"75";
reg<=x"6C";
reg<=x"74";
reg<=x"69";
reg<=x"70";
reg<=x"6C";
reg<=x"69";
reg<=x"63";
reg<=x"61";
reg<=x"74";
reg<=x"69";
reg<=x"6F";
reg<=x"6E";
reg<=x"0D";
reg<=x"0A";
--Division
when S9 => reg<=x"44";
reg<=x"69";
reg<=x"76";
reg<=x"69";
reg<=x"73";
reg<=x"69";
reg<=x"6F";
reg<=x"6E";
reg<=x"0D";
reg<=x"0A";
--Non-valid char
when others => reg<=x"4E";
reg<=x"6F";
reg<=x"6E";
reg<=x"2D";
reg<=x"76";
reg<=x"61";
reg<=x"6C";
reg<=x"69";
reg<=x"64";
reg<=x"20";
reg<=x"43";
reg<=x"68";
reg<=x"61";
reg<=x"72";
reg<=x"0D";
reg<=x"0A";
end case;
end if;
dready_transmitter <= '1'; -- indicate with a HIGH to the transmitter that no byte will be sent
end process;
sendtotransmitter <= reg;
end design;