------------------MAIN MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(
start_stop, reset, clk: in STD_LOGIC;
led: out STD_LOGIC_VECTOR (6 downto 0)
);
end counter;
architecture Behavioral of counter is
signal temp: std_logic_vector (7 downto 0);
signal cp_o: std_logic;
begin
S1: entity work.FreqDivGen generic map (1000000) port map (cp, cp_o);
process(cp_o, reset, start_stop)
begin
if(reset = '1') then
temp <= "00111011";
elsif(cp_o'event and cp_o = '1') then
if(temp = '0') then
temp <= "00111011";
end if;
if(start_stop = '1') then
temp <= temp - 1;
else
temp <= temp;
end if;
end if;
end process;
with temp select
led<= "0000001" when "0000", --0 (abcdefg)
"1111001" when "0001", --1
"0010010" when "0010", --2
"0000110" when "0011", --3
"1001100" when "0100", --4
"0100100" when "0101", --5
"0100000" when "0110", --6
"0001111" when "0111", --7
"0000000" when "1000", --8
"0000100" when "1001", --9
"0001000" when "1010", --a
"1100000" when "1011", --b
"0110001" when "1100", --c
"1000010" when "1101", --d
"0110000" when "1110", --e
"0111000" when others; --f
end Behavioral;
-----------------------------------
---------------------FREQDIVGEN MODULE
--------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------
entity FreqDivGen is
generic(nfCLK: natural := 100);
port(
clk: in STD_LOGIC := '0';
clk_o: buffer STD_LOGIC := '0'
);
end FreqDivGen;
architecture Behavioral of FreqDivGen is
begin
process(clk)
variable temp: integer range 0 to nfCLK/2 := 0;
begin
if (clk'event and clk='1') then
temp:=temp+1;
if (temp>=nfCLK/2) then
clk_o<=not clk_o;
temp:=0;
end if;
end if;
end process;
end Behavioral;
-----------------------------------