[VHDL] Needed help with frequency divider

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marcin1135

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HI all.
I have some problems with frequency divider. I have divider 5MHz -> 2Hz.

Code: 
signal CONTENT: std_logic_vector(21 downto 0):= "0000000000000000000000";
begin
process (CLK5MHZ_IN)
begin
if rising_edge(CLK5MHZ_IN) then
if CONTENT(20 downto 0) = "111111111111111111111" then
CONTENT <= not CONTENT(21) & "000000000000000000000";
else CONTENT <= CONTENT + 1;
end if;
end if;
end process;
CLK2HZ_OUT <= CONTENT(21);

I need frequency: 1Hz and 5Hz.
Please help me with this issue. I will be grateful for any sugestions.

regards
Martin:!:
 

In my opinion you can realize it as:
if rising_edge(clk) then CONTENT<=CONTENT+1;
end if;
end processs;
CLK2HZ<=CONTENT(21);
CLK5HZ<=CONTENT(20);
 

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