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VHDL/module get different simulation result as a component

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ennian

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I have a module with one architecture and in the behavioral simulation, I get the result that I want.

But when I use an instance of this module in a new module, the simulation(with the same input values, Ive checked the intern signals) gives a different result (the output is one cycle delayed).

Can anyone help me?
 

benradu

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Re: VHDL/module get different simulation result as a compone

Your stimulus are not exactly the same. When you simulate the stand alone component your stimulus which are probably synchronous with the clock are applied a little before the active edge of your clock (depending on your testbench setup).
When you simulate the component in a system your "stimulus" to the component are generated by the surrounding logic, and appear right after the active edge. Therefore you see a clock delay in the simulation result. Since you do behavioral simulation you don't see those delays.
 

ennian

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Re: VHDL/module get different simulation result as a compone

Thank u for your reply. And you're right. And actually even in the behavioral simulation I can see the slight delay in the input for the component.
 

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