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VHDL MOD_800 Counter Help!

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Gerry_robotics

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Giday Folks,

Working on a VHDL MOD_800 Counter and have come up with a few Design Warnings when I run it through the Design Checker.
I would like to resolve them if at all possible.

The Warnings are as follows:

WARNING:
Internally generated reset in top design unit 'MOD_800_nty' is not isolated at the top level.

WARNING:
Synchronous reset of counter 'h_count' in top design unit 'MOD_800_nty' is internally generated.


My VHDL Code is shown below for the Counter:

Code:
-
-- VHDL Architecture LAB_02_lib.MOD_800_nty.MOD_800_arch
--
-- Created:
--          by - Gerry.UNKNOWN (VIDEO)
--          at - 14:22:23 03/ 1/2012
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY MOD_800_nty IS
   PORT(
                Por : IN std_logic;
          clk_25Mhz : IN std_logic;    
    Char_Addr_Lines : OUT std_logic_vector(9 downto 0)
        );


END MOD_800_nty ;

ARCHITECTURE MOD_800_arch OF MOD_800_nty IS
signal h_count : std_logic_vector(9 downto 0); -- 10 BIT Binary counter (1024 states) is needed to count to 799

BEGIN 
Char_Addr_Lines <= h_count;


----------------------------------------- COUNTER PROCESS ----------------------------------------------------
--------------------------------------------------------------------------------------------------------------

process (clk_25Mhz, Por)
Begin

                          
 if (Por = '1') then                                                                        -- reset button
         h_count <= "0000000000";                                                           -- reset to 0


     elsif ((clk_25Mhz 'event and clk_25Mhz = '1') and h_count = "1100011111") then        -- on the rising edge & when you get to 799 reset to 0
            h_count <= "0000000000";

     elsif (clk_25Mhz 'event and clk_25Mhz = '1') then                                      -- OtherwiseoOn Rising Edge of the CLock Advance the counter by 1
            h_count <= h_count + 1;

 end if;


end process;


-------------------------------------------------------------------------------------------------------------

END ARCHITECTURE MOD_800_arch;

Any advice would be appreciated,

Regards,
Gerry
 

imbichie

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Hi,

You can modified the code like this..

Code:
-
-- VHDL Architecture LAB_02_lib.MOD_800_nty.MOD_800_arch
--
-- Created:
--          by - Gerry.UNKNOWN (VIDEO)
--          at - 14:22:23 03/ 1/2012
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY MOD_800_nty IS
   PORT(
                Por : IN std_logic;
          clk_25Mhz : IN std_logic;    
    Char_Addr_Lines : OUT std_logic_vector(9 downto 0)
        );


END MOD_800_nty ;

ARCHITECTURE MOD_800_arch OF MOD_800_nty IS
signal h_count : std_logic_vector(9 downto 0); -- 10 BIT Binary counter (1024 states) is needed to count to 799

BEGIN 
Char_Addr_Lines <= h_count;


----------------------------------------- COUNTER PROCESS ----------------------------------------------------
--------------------------------------------------------------------------------------------------------------

process (clk_25Mhz, Por)
Begin               
	if (Por = '1') then                                                                        -- reset button
         h_count <= "0000000000";                                                      -- reset to 0
    elsif (rising_edge(clk_25Mhz)) then
		if  (h_count = "1100011111") then        -- on the rising edge & when you get to 799 reset to 0
            h_count <= "0000000000";
		else								-- OtherwiseoOn Rising Edge of the CLock Advance the counter by 1
            h_count <= h_count + 1;
		end if;
	end if;
end process;


-------------------------------------------------------------------------------------------------------------

END ARCHITECTURE MOD_800_arch;

But the warnings may not remove.....

The warnings are at the place of instantiation...

May be the warnings are due to the reset connected to this MOD_800_nty...

Can you pls post the code where this module instantiated..
 

Gerry_robotics

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I made those Changes you suggested, and as you suspected the Warnings are still the same.

The code I created from scratch, so it's frustrating when these Warnings pop up.


I'm using Mentor Graphics HDL Designer software, as the code indicates. It generates an initial blank project template
with standard libraries, an architecture and entity all set up waiting for declarations. It's quite handy actually.

Any other suggestions?

Thanks so much for your help.
-Gerry
 

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