[vhdl] key word "unaffected", howto use it?

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vvsvv

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unaffected vhdl

May any body tell me howto use the "unaffected" word ??

may I :

.....
case vref is
when '1' =>
addr_wr_hori <= 0 ;
when '0' => addr_wr_hori <= addr_wr_hori + 1 ;
when others => unaffected;


...................
thanks!
 

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