port(
x:in std_logic;
y:in integer range 0 to 32;
zut integer range 0 to 32;
w: out std_logic);
For the simple above entiy I get the following error:
Line 17: ERROR, Non-Standard IEEE type "integer", used for port "y"
Line 17: ERROR, VITAL Top-Level port "y" has a "integer" type mark that does not denote a type/subtype declared in package std_logic_1164
Line 17: WARNING, Dimension/Range definition "(0 to 32)", for "y", does not comply to descending order convention
Using integer types for top level ports may be supported by your VHDL tool. In synthesizable designs, the mapping of integer to port bits is implementation dependant.
As a more simple reason, you possibly didn't import a numeric library.
I don't see that using a package with a type definition changes anything. Integer type in top level ports is supported by some synthesis tools, e.g. A.ltera Q.uartus, but apparently unsupported by some others. That's O.K., because the VHDL standard doesn't require it, as far as I understand.