This question is primarily related to the problem associated with doing if statement with non-nibble sized words.
for example
Code VHDL - [expand]
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signal sig :std_logic_vector(5downto0);if sig =(others=> '0')then-- will not work, because the condition is unconstrained.if sig =(sig'range=> '0')then-- will work, because the condition is constrained.
Now what if I wanted to do an if statement on the signal, where every bit must be of one value, but bit 1, 3, 5 for example must be another value.
Lets assume that the signal to under go a conditional check is huge and that it would take a long time for a human to work out (I don't have the integer value for to_unsigned(I, sig'length) command) the total signal value. Therefore, the most practical solution would be to do
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constant c_condition :std_logic_vector(121downto0):=(5=> '0', 3=> '0', 1=>'0', others=> '1');signal sig :std_logic_vector(121downto0)if sig = c_condition then
However in my quest to take laziness to a whole new level, I don't want to have to declare a constant to use it in the condition. Is there a way I can go straight to the if statement.
Re: vhdl if statements making portable condition for non nibble sized words
No
Using a constant is the easiest, and at 1 extra line, isnt much of a burden.
Other than the constant, the only other way would be some sort of function, but thats way more complicated that just a constant, and likely to need a constant anyway.