megaqujik
Newbie level 1
vhdl i2c master slave
hi everybody
i am trying to write i2c master controller in vhdl and i am a bit confused :/ I know there is discussion in this forum from 2005 about it, but there is not clear explanation. I know protocol but i am not sure tha signal state i am using are correct. So i do it this way:
About SCL all is claer ofcourse.
If i want to write to SDA i just do
SDA <= '0' or SDA <= '1'.
What should i do when i need read from slave( acknowledge and data )? i2c protocol description tells to release SDA setting it to high. In vhdl should I set it to 'Z'? What is diffrent between 'z' and 'h' ? I know that 'z' connected to pull up resistor can be interpreted as '1'.
So if bit 9 ( reading ackwnoledge from slave) coming should i set SDA to 'Z' during SCL low and simply check if SDA='0' during SCL high?
Please ask for further information if needed.
PS: If my english is bad - sorry
Best Regards
Michael
hi everybody
i am trying to write i2c master controller in vhdl and i am a bit confused :/ I know there is discussion in this forum from 2005 about it, but there is not clear explanation. I know protocol but i am not sure tha signal state i am using are correct. So i do it this way:
About SCL all is claer ofcourse.
If i want to write to SDA i just do
SDA <= '0' or SDA <= '1'.
What should i do when i need read from slave( acknowledge and data )? i2c protocol description tells to release SDA setting it to high. In vhdl should I set it to 'Z'? What is diffrent between 'z' and 'h' ? I know that 'z' connected to pull up resistor can be interpreted as '1'.
So if bit 9 ( reading ackwnoledge from slave) coming should i set SDA to 'Z' during SCL low and simply check if SDA='0' during SCL high?
Please ask for further information if needed.
PS: If my english is bad - sorry
Best Regards
Michael