[vhdl ] how to deal with unused state in FSM? thank!!

[vvsvv]

I may use 5 states-- s0 s1 s2 s3 s4,

synthesis may use 000 001 010 011 100 to represent them ,

If I dont care the other 3 unused states (101,110,111), I think there may some unwanted things happen.

so I think I must do something to deal with the unused stateS!

but HOW ? :arrow:
thanks!!!

 

[Husoo]

use them!
i mean to say that you should get them connected into the state machine flow. for example, if the SM steps into one of the unwanted states, make a transition into the reset or even better a known state to signal this problem.
however, maybe..., better solution to code the states in gray - if it possible at all, - to avoid unwanted state. In this case, only valid states can occur.

 

[tlp71@hotmail.com]

if you use the case costruct to resolve you state machine , you must use the case when others, and set NULL; or what do you like.
Be.
G.

 

[ashishjindal76]

if u use case statement i thik that unwanted states will never occour. then there is no question of irregularities with the output. usinf if statement or ant other statement u should use in such a way that undefined states will never occour. u dont have to worry abt them.

bye
ashish

 

[rol73]

The unwanted states of a state machine can EVER occur (even if you use a case structure), due to signal glitchs, various mismatchs, etc etc...

The problem is: if your state machine goes in an unwanted state, what happens after? the machine can recover from this condition?

A good coding practice is to provide in each case a resolution way from an unwanted state to a known state...

 

[v_kumar]

for 5 state u have to use 3bit binary number but its combination will give u more than 5 states so one way is to assign all unused states to some value,
or
give a defalt state.ie when the process goes from state s0-->s5 after s5 assign a state to which it has to return

 

[fletcher]

In theory these states must not happen but in practice your system will experience some of them due to practical problem like glitchs, signal race,...In each case your system must be able to go to a known state and if it is critical you must reset your system.

 

[ieee]

You need describe them for your system stability. Check Verilog / VHDL LRM