VHDL highest possible integer

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
function decimal_string_bits_needed(decimal_string: string) return natural is
constant maximum_bitwidth: positive := 512;
variable tmp_unsigned: unsigned(maximum_bitwidth+3 downto 0) := (others => '0'); -- 4 extra bits to detect overflow
variable character_value: integer;
begin
  for string_pos in decimal_string'range loop
    case decimal_string(string_pos) is
      when '0' => character_value := 0;
      when '1' => character_value := 1;
      when '2' => character_value := 2;
      when '3' => character_value := 3;
      when '4' => character_value := 4;
      when '5' => character_value := 5;
      when '6' => character_value := 6;
      when '7' => character_value := 7;
      when '8' => character_value := 8;
      when '9' => character_value := 9;
      when others => report("Illegal number") severity failure;
    end case;
    tmp_unsigned := tmp_unsigned(maximum_bitwidth-1 downto 0) * to_unsigned(10, 4);
    tmp_unsigned := tmp_unsigned + character_value;
    if tmp_unsigned(maximum_bitwidth+3 downto maximum_bitwidth) /= "0000" then
      report("Too large number") severity failure;
    end if;
  end loop;
  
  for i in tmp_unsigned'range loop
    if tmp_unsigned(i) = '1' then
      return i+1;
    end if;
  end loop;
  return 1;
end decimal_string_bits_needed;